The LM25066A combines a high-performance hot-swap controller with a PMBus™ compliant SMBus/I2C interface to accurately measure, protect and control the electrical operating conditions of computing and storage blades connected to a backplane power bus. The LM25066A continuously supplies real-time power, voltage, current, temperature and fault data to the system management host via the SMBus interface.
The LM25066A control block includes a unique hot-swap architecture that provides current and power limiting to protect sensitive circuitry during insertion of boards into a live system backplane, or any other hot power source. A fast acting circuit breaker prevents damage in the event of a short circuit on the output. The input undervoltage and overvoltage levels and hysteresis are configurable, as well as the insertion delay time and fault detection time. A temperature monitoring block on the LM25066A interfaces with a low-cost external diode for monitoring the temperature of the external MOSFET or other thermally sensitive components. The POWER GOOD output provides a fast indicator when the input and/or output voltages are outside their programmed range. LM25066A current measurement accuracy is ±1% over temperature.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
LN25066A | WQFN (24) | 5.00 mm × 4.00 mm |
Changes from F Revision (February 2013) to G Revision
Changes from E Revision (February 2013) to F Revision
The LM25066A monitoring block computes both the real-time and average values of subsystem operating parameters (VIN, IIN, PIN, VOUT) as well as the peak power. Accurate power averaging is accomplished by averaging the product of the input voltage and current. A black box (Telemetry/Fault Snapshot) function captures and stores telemetry data and device status in the event of a warning or a fault.
PIN | TYPE | DESCRIPTION | |
---|---|---|---|
NO. | NAME | ||
1 | ADR2 | SMBUS address line 2 | 3 - state address line. Should be connected to GND, VDD, or left floating. |
2 | ADR1 | SMBUS address line 1 | 3 - state address line. Should be connected to GND, VDD, or left floating. |
3 | ADR0 | SMBUS address line 0 | 3 - state address line. Should be connected to GND, VDD, or left floating. |
4 | VDD | Internal sub-regulator output | Internally sub-regulated 4.5-V bias supply. Connect a 1-µF capacitor on this pin to ground for bypassing. |
5 | CL | Current limit range | Connect this pin to GND to set the nominal overcurrent threshold at 25 mV. Connecting CL to VDD sets the overcurrent threshold to be 46 mV. |
6 | CB | Circuit breaker range | This pin sets the circuit breaker protection point in relation to the overcurrent trip point. When connected to GND, this pin sets the circuit breaker point to be 1.8 times the overcurrent threshold. Connecting this pin to VDD sets the circuit breaker trip point to be 3.6 times the overcurrent threshold. |
7 | FB | Power Good feedback | An external resistor divider from OUT sets the output voltage at which the PGD pin switches. The threshold at the pin is 1.167 V. An internal 24-µA current source provides hysteresis. |
8 | RETRY | Fault retry input | This pin configures the power up fault retry behavior. When this pin is grounded, the device continually tries to engage power during a fault. If the pin is connected to VDD, the device will latch off during a fault. |
9 | TIMER | Timing capacitor | An external capacitor connected to this pin sets the insertion time delay, fault timeout period and restart timing. |
10 | PWR | Power limit set | An external resistor connected to this pin, in conjunction with the current sense resistor (RS), sets the maximum power dissipation allowed in the external series pass MOSFET. |
11 | PGD | Power Good indicator | An open drain output. This output is high when the voltage at the FB pin is above 1.167 V and the input supply is within its undervoltage and overvoltage thresholds. Connect through a pullup resistor to the output rail (external MOSFET source) or any other voltage to be monitored. |
12 | OUT | Output feedback | Connect to the output rail (external MOSFET source). Internally used to determine the MOSFET VDS voltage for power limiting, and to monitor the output voltage. |
13 | GATE | Gate drive output | Connect to the external MOSFET's gate. |
14 | SENSE | Current sense input | The voltage across the current sense resistor (RS) is measured from VIN to this pin. If the voltage across RS reaches overcurrent threshold, the load current is limited and the fault timer activates. |
15 | VIN | Positive supply input | A small ceramic bypass capacitor close to this pin is recommended to suppress transients which occur when the load current is switched off. |
16 | UVLO/EN | Under-voltage lockout | An external resistor divider from the system input voltage sets the undervoltage turnon threshold. An internal 23-µA current source provides hysteresis. The enable threshold at the pin is 1.16 V. This pin can also be used for remote shutdown control. |
17 | OVLO | Over-voltage lockout | An external resistor divider from the system input voltage sets the overvoltage turnoff threshold. An internal 23-µA current source provides hysteresis. The disable threshold at the pin is 1.16 V. |
18 | GND | Circuit ground | |
19 | SDA | SMBus data pin | Data pin for SMBus. |
20 | SCL | SMBus clock | Clock pin for SMBus. |
21 | SMBA | SMBus alert line | Alert pin for SMBus, active low. |
22 | VREF | Internal Reference | Internally generated precision 2.73-V reference used for analog to digital conversion. Connect a 1-µF capacitor on this pin to ground for bypassing. |
23 | DIODE | External diode | Connect this to a diode-configured NPN transistor for temperature monitoring. |
24 | VAUX | Auxiliary voltage input | Auxiliary pin allows voltage telemetry from an external source. Full scale input of 1.16 V. |
Pad | Exposed Pad | Exposed pad of WQFN package | No internal electrical connections. Solder to the ground plane to reduce thermal resistance. |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Input voltage | VIN, SENSE to GND (2) | –0.3 | 24 | V |
GATE, FB, UVLO/EN, OVLO, PGD to GND (2) | –0.3 | 20 | V | |
OUT to GND | –1 | 20 | V | |
SCL, SDA, SMBA, CL, CB, ADR0, ADR1, ADR2, VDD, VAUX, DIODE, RETRY to GND | –0.3 | 6 | V | |
VIN to SENSE | –0.3 | 0.3 | V | |
Junction Temperature, TJ | 150 | °C | ||
Storage temperature, Tstg | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM) (1) | ±2000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±500 |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
VIN, SENSE, OUT voltage | 2.9 | 17 | V | ||
VDD | 2.9 | 5.5 | V | ||
Junction temperature, TJ | –40 | 125 | °C |
THERMAL METRIC(1) | LM25066A | UNIT | |
---|---|---|---|
NHZ (WQFN) | |||
24 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 34.1 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 28.9 | °C/W |
RθJB | Junction-to-board thermal resistance | 13.4 | °C/W |
ψJT | Junction-to-top characterization parameter | 0.3 | °C/W |
ψJB | Junction-to-board characterization parameter | 13.5 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 3.6 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
INPUT (VIN PIN) | ||||||
IIN-EN | Input current, enabled | UVLO = 2 V and OVLO = 0.7 V | 5.8 | 8 | mA | |
POR | Power on reset threshold at VIN | VIN increasing | 2.6 | 2.8 | V | |
PORHYS | POREN hysteresis | VIN decreasing | 150 | mV | ||
VDD REGULATOR (VDD PIN) | ||||||
VDD | IVDD = 5 mA, VIN = 12 V | 4.3 | 4.5 | 4.7 | V | |
IVDD = 5 mA, VIN = 4.5 V | 3.5 | 3.9 | 4.3 | V | ||
VDDILIM | VDD current limit | 25 | 45 | mA | ||
UVLO/EN, OVLO PINS | ||||||
UVLOTH | UVLO threshold | VUVLO Falling | 1.147 | 1.16 | 1.173 | V |
UVLOHYS | UVLO hysteresis current | UVLO = 1 V | 18 | 23 | 28 | µA |
UVLODEL | UVLO delay | Delay to GATE high | 8 | µs | ||
Delay to GATE low | 20 | |||||
UVLOBIAS | UVLO bias current | UVLO = 3 V | 1 | µA | ||
OVLOTH | OVLO threshold | VOVLO rising | 1.141 | 1.16 | 1.185 | V |
OVLOHYS | OVLO hysteresis current | OVLO = 1 V | –28 | –23 | –18 | µA |
OVLODEL | OVLO delay | Delay to GATE high | 19 | µs | ||
Delay to GATE low | 9 | |||||
OVLOBIAS | OVLO bias current | OVLO = 1 V | 1 | µA | ||
POWER GOOD (PGD PIN) | ||||||
PGDVOL | Output low voltage | ISINK = 2 mA | 25 | 60 | mV | |
PGDIOH | Off leakage current | VPGD = 17 V | 1 | µA | ||
PGDDELAY | Power Good delay | VFB to VPG | 115 | ns | ||
FB PIN | ||||||
FBTH | FB threshold | VFB rising | 1.141 | 1.167 | 1.19 | V |
FBHYS | FB hysteresis current | –31 | –24 | –18 | µA | |
FBLEAK | Off leakage current | VFB = 1 V | 1 | µA | ||
POWER LIMIT (PWR PIN) | ||||||
PWRLIM | Power limit sense voltage (VIN-SENSE) | SENSE-OUT = 12 V, RPWR = 25 kΩ | 9 | 12.5 | 15 | mV |
IPWR | PWR pin current | VPWR = 2.5 V | –10 | µA | ||
RSAT(PWR) | PWR pin impedance when disabled | UVLO = 0.7 V | 180 | Ω | ||
GATE CONTROL (GATE PIN) | ||||||
IGATE | Source current | Normal operation | –28 | –22 | –16 | µA |
Fault sink current | UVLO = 1 V | 1.5 | 2 | 2.5 | mA | |
POR circuit breaker sink current | VIN - SENSE = 150 mV or VIN < RPOR, VGATE = 5 V | 105 | 190 | 275 | mA | |
VGATE | Gate output voltage in normal operation | GATE voltage with respect to ground | 17 | 18.8 | 20.3 | V |
OUT PIN | ||||||
IOUT-EN | OUT bias current, enabled | OUT = VIN, normal operation | 16 | µA | ||
IOUT-DIS | OUT bias current, disabled(2) | Disabled, OUT = 0 V, SENSE = VIN | –12 | µA | ||
CURRENT LIMIT | ||||||
VCL | Threshold voltage | CL = GND | 22.5 | 25 | 27 | mV |
CL = GND, TJ = 10°C to 85°C | 23 | 25 | 27 | |||
CL = VDD | 42.3 | 46 | 49.7 | |||
ISENSE | SENSE input current | Enabled, SENSE = OUT | 33 | µA | ||
Disabled, OUT = 0 V | 46 | |||||
Enabled, OUT = 0 V | 45 | |||||
CIRCUIT BREAKER | ||||||
VCB | Threshold voltage × 1.8 | VIN - SENSE, CL = GND, CB = GND | 35 | 45 | 55 | mV |
CB:CL ratio | CB = GND | 1.6 | 1.8 | 2 | ||
VCB | Threshold voltage × 3.6 | VIN - SENSE, CL = GND, CB = VDD | 70 | 90 | 110 | mV |
CB:CL ratio | CB = VDD | 3.1 | 3.6 | 4 | ||
TIMER (TIMER PIN) | ||||||
VTMRH | Upper threshold | 1.54 | 1.7 | 1.85 | V | |
VTMRL | Lower threshold | Restart cycles | 0.85 | 1 | 1.07 | V |
End of 8th cycle | 0.3 | V | ||||
Re-enable threshold | 0.3 | V | ||||
ITIMER | Insertion time current | TIMER pin = 2 V | –3 | –5.5 | –8 | µA |
Sink current, end of insertion time | 1.4 | 1.9 | 2.4 | mA | ||
Fault detection current | –120 | –90 | –60 | µA | ||
Fault sink current | 2.8 | µA | ||||
DCFAULT | Fault restart duty cycle | 0.67% | ||||
INTERNAL REFERENCE | ||||||
VREF | Reference voltage | 2.703 | 2.73 | 2.757 | V | |
ADC AND MUX | ||||||
Resolution | 12 | Bits | ||||
INL | Integral non-linearity | ADC only | ±1 | LSB | ||
TELEMETRY ACCURACY | ||||||
IINFSR | Current input full scale range | CL = GND | 30.2 | mV | ||
CL = VDD | 60.4 | mV | ||||
IINLSB | Current input LSB | CL = GND | 7.32 | µV | ||
CL = VDD | 14.64 | µV | ||||
VAUXFSR | VAUX input full scale range | 1.16 | V | |||
VAUXLSB | VAUX input LSB | 283.2 | µV | |||
VINFSR | Input voltage full scale range | 18.7 | V | |||
VINLSB | Input voltage LSB | 4.54 | mV | |||
IINACC | Input current accuracy | VIN – SENSE = 25 mV, CL = GND | –1.2% | 1% | ||
VIN – SENSE = 25 mV, CL = GND TJ = 10°C to 85°C |
–1% | 1% | ||||
VIN – SENSE = 50 mV, CL = VDD | –1.8% | 1.8% | ||||
VIN – SENSE = 50 mV, CL = GND TJ = 10°C to 85°C |
–5% | 5% | ||||
VACC | VAUX, VIN, VOUT accuracy | VIN, VOUT = 12 V VAUX = 1 V |
–1% | 1.2% | ||
VIN, VOUT = 12 V VAUX = 1 V TJ = 10°C to 85°C |
–1% | 1% | ||||
PINACC | Input power accuracy | VIN = 12 V, VIN – SENSE = 25 mV, CL = GND |
–2.3% | 2% | ||
VIN = 12 V, VIN – SENSE = 25 mV, CL = GND, TJ = 10°C to 85°C |
–2% | 2% | ||||
REMOTE DIODE TEMPERATURE SENSOR | ||||||
TACC | Temperature accuracy using local diode | TA = 10°C to 85°C | 2 | 10 | °C | |
Remote diode resolution | 9 | bits | ||||
IDIODE | External diode current source | High level | 250 | 300 | µA | |
Low level | 9.4 | µA | ||||
Diode current ratio | 26 | |||||
PMBUS PIN THRESHOLDS (SMBA, SDA, SCL) | ||||||
VIL | Data, clock input low voltage | 0.8 | V | |||
VIH | Data, clock input high voltage | 2.1 | 5.5 | V | ||
VOL | Data output low voltage | IPULLUP = 500 µA | 0 | 0.4 | V | |
ILEAK | Input leakage current | SDA, SMBA, SCL = 5 V | 1 | µA | ||
CONFIGURATION PIN THRESHOLDS (CB, CL, RETRY) | ||||||
VIH | Threshold voltage | 3 | V | |||
ILEAK | Input leakage current | CL, CB, RETRY = 5 V | 1 | mA |
MIN | MAX | UNIT | ||
---|---|---|---|---|
FSMB | SMBus Operating Frequency | 10 | 400 | kHz |
TBUF | Bus free time between Stop and Start Condition | 1.3 | µs | |
THD:STA | Hold time after (Repeated) Start Condition. After this period, the first clock is generated. | 0.6 | µs | |
TSU:STA | Repeated Start Condition setup time | 0.6 | µs | |
TSU:STO | Stop Condition setup time | 0.6 | µs | |
THD:DAT | Data hold time | 300 | ns | |
TSU:DAT | Data setup time | 100 | ns | |
TTIMEOUT | Clock low timeout(1) | 25 | 35 | ms |
TLOW | Clock low period | 1.5 | µs | |
THIGH | Clock high period(2) | 0.6 | µs | |
TLOW:SEXT | Cumulative clock low extend time (slave device)(3) | 25 | ms | |
TLOW:MEXT | Cumulative low extend time (master device)(4) | 10 | ms | |
TF | Clock or Data Fall Time(5) | 20 | 300 | ns |
TR | Clock or Data Rise Time(5) | 20 | 300 | ns |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
CURRENT LIMIT | |||||||
tCL | Response time | VIN-SENSE stepped from 0 mV to 80 mV | 1.2 | µs | |||
CIRCUIT BREAKER | |||||||
tCB | Response time | VIN - SENSE stepped from 0 mV to 150 mV, time to GATE low, no load | TJ = –40°C to 85°C | 0.6 | 1.2 | µs | |
TIMER (TIMER PIN) | |||||||
tFAULT_DELAY | Fault to GATE low delay | TIMER pin reaches the upper threshold | 17 | µs | |||
ADC AND MUX | |||||||
tAQUIRE | Acquisition + Conversion Time | Any channel | 100 | µs | |||
tRR | Acquisition Round Robin Time | Cycle all channels | 1 | ms |