SNVS509F April   2007  – November 2023 LM25116

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 High-Voltage Start-Up Regulator
      2. 6.3.2 Enable
      3. 6.3.3 UVLO
      4. 6.3.4 Oscillator and Sync Capability
      5. 6.3.5 Error Amplifier and PWM Comparator
      6. 6.3.6 Ramp Generator
      7. 6.3.7 Current Limit
      8. 6.3.8 HO Output
      9. 6.3.9 Thermal Protection
    4. 6.4 Device Functional Modes
      1. 6.4.1 Soft Start and Diode Emulation
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1  Timing Resistor
        2. 7.2.2.2  Output Inductor
        3. 7.2.2.3  Current Sense Resistor
        4. 7.2.2.4  Ramp Capacitor
        5. 7.2.2.5  Output Capacitors
        6. 7.2.2.6  Input Capacitors
        7. 7.2.2.7  VCC Capacitor
        8. 7.2.2.8  Bootstrap Capacitor
        9. 7.2.2.9  Soft Start Capacitor
        10. 7.2.2.10 Output Voltage Divider
        11. 7.2.2.11 UVLO Divider
        12. 7.2.2.12 MOSFETs
        13. 7.2.2.13 MOSFET Snubber
        14. 7.2.2.14 Error Amplifier Compensation
        15. 7.2.2.15 Comprehensive Equations
          1. 7.2.2.15.1 Current Sense Resistor and Ramp Capacitor
          2. 7.2.2.15.2 Modulator Transfer Function
          3. 7.2.2.15.3 Error Amplifier Transfer Function
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.2.2.14 Error Amplifier Compensation

RCOMP, CCOMP and CHF configure the error amplifier gain characteristics to accomplish a stable voltage loop gain. One advantage of current mode control is the ability to close the loop with only two feedback components, RCOMP and CCOMP. The voltage loop gain is the product of the modulator gain and the error amplifier gain. For the 5-V output design example, the modulator is treated as an ideal voltage-to-current converter. The DC modulator gain of the LM25116 can be modeled with Equation 33.

Equation 33. DC Gain(MOD) = RLOAD / (A × RS)

The dominant low frequency pole of the modulator is determined by the load resistance (RLOAD) and output capacitance (COUT). The corner frequency of this pole is calculated with Equation 34.

Equation 34. fP(MOD) = 1 / (2π × RLOAD × COUT)

For RLOAD = 5 V / 7 A = 0.714 Ω and COUT = 320 µF (effective) then fP(MOD) = 700 Hz

DC Gain(MOD) = 0.714 Ω / (10 × 10 mΩ) = 7.14 = 17 dB

For the 5-V design example, the modulator gain versus frequency characteristic was measured as shown in Figure 7-3.

GUID-F27530F2-55A5-4825-9F20-786444E4ABAC-low.pngFigure 7-3 Modulator Gain and Phase

Components RCOMP and CCOMP configure the error amplifier as a type II configuration. The DC gain of the amplifier is 80 dB which has a pole at low frequency and a zero at fZEA = 1 / (2π x RCOMP × CCOMP). The error amplifier zero cancels the modulator pole leaving a single pole response at the crossover frequency of the voltage loop. A single pole response at the crossover frequency yields a very stable loop with 90° of phase margin. For the design example, a target loop bandwidth (crossover frequency) of one-tenth the switching frequency or 25 kHz was selected. The compensation network zero (fZEA) must be selected at least an order of magnitude less than the target crossover frequency. This constrains the product of RCOMP and CCOMP for a desired compensation network zero 1 / (2π × RCOMP × CCOMP) to be 2.5 kHz. Increasing RCOMP, while proportionally decreasing CCOMP, increases the error amp gain. Conversely, decreasing RCOMP while proportionally increasing CCOMP, decreases the error amp gain. For the design example, CCOMP was selected as 3300 pF and RCOMP was selected as 18 kΩ. These values configure the compensation network zero at 2.7 kHz. The error amp gain at frequencies greater than fZEA is: RCOMP / RFB2, which is approximately 4.8 (13.6 dB).

GUID-025FFCFF-6B7C-465E-A49C-668444391097-low.pngFigure 7-4 Error Amplifier Gain and Phase

The overall voltage loop gain can be predicted as the sum (in dB) of the modulator gain and the error amp gain.

GUID-3ACC6CDB-CA31-4B91-B816-E16A019EE5EA-low.pngFigure 7-5 Overall Voltage Loop Gain and Phase

If a network analyzer is available, the modulator gain can be measured and the error amplifier gain can be configured for the desired loop transfer function. If a network analyzer is not available, the error amplifier compensation components can be designed with the guidelines given. Step load transient tests can be performed to verify acceptable performance. The step load goal is minimum overshoot with a damped response. CHF can be added to the compensation network to decrease noise susceptibility of the error amplifier. The value of CHF must be sufficiently small because the addition of this capacitor adds a pole in the error amplifier transfer function. This pole must be well beyond the loop crossover frequency. A good approximation of the location of the pole added by CHF is: fP2 = fZEA × CCOMP / CHF. The value of CHF was selected as 100 pF for the design example.