SNVS680I August   2010  – April 2018 LM25119

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Typical Application Circuit
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  High Voltage Start-Up Regulator
      2. 7.3.2  UVLO
      3. 7.3.3  Enable 2
      4. 7.3.4  Oscillator and Sync Capability
      5. 7.3.5  Error Amplifiers and PWM Comparators
      6. 7.3.6  Ramp Generator
      7. 7.3.7  Current Limit
      8. 7.3.8  Hiccup Mode Current Limiting
      9. 7.3.9  Soft Start
      10. 7.3.10 HO and LO Output Drivers
      11. 7.3.11 Maximum Duty Cycle
      12. 7.3.12 Thermal Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Diode Emulation
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Miscellaneous Functions
      2. 8.1.2 Interleaved Two-Phase Operation
      3. 8.1.3 Interleaved 4-Phase Operation
    2. 8.2 Typical Applications
      1. 8.2.1 Dual-output Design Example
        1. 8.2.1.1 Design Requirements
          1. 8.2.1.1.1 External Components
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1  Timing Resistor
          2. 8.2.1.2.2  Output Inductor
          3. 8.2.1.2.3  Current Sense Resistor
          4. 8.2.1.2.4  Ramp Resistor and Ramp Capacitor
          5. 8.2.1.2.5  Output Capacitors
          6. 8.2.1.2.6  Input Capacitors
          7. 8.2.1.2.7  VCC Capacitor
          8. 8.2.1.2.8  Bootstrap Capacitor
          9. 8.2.1.2.9  Soft Start Capacitor
          10. 8.2.1.2.10 Restart Capacitor
          11. 8.2.1.2.11 Output Voltage Divider
          12. 8.2.1.2.12 UVLO Divider
          13. 8.2.1.2.13 MOSFET Selection
          14. 8.2.1.2.14 MOSFET Snubber
          15. 8.2.1.2.15 Error Amplifier Compensation
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Two-Phase Design Example
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Switching Jitter Root Causes and Solutions
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Community Resources
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.1.2.3 Current Sense Resistor

Before determining the value of current sense resistor (RS), it is valuable to understand the K factor, which is the ramp slope multiple chosen for slope compensation. The K factor can vary from 1 to 3 in practice and is defined with Equation 12.

Equation 12. LM25119 30126233.gif

The performance of the converter varies depending on the selected K value (see Table 1). For this example, 3 was chosen as the K factor to minimize the power loss in sense resistor RS and the cross-talk between channels. Crosstalk between the two regulators under certain conditions is observed on the output as switch jitter.

The maximum output current capability (IOUT(MAX)) must be about 20% to 50% higher than the required output current, (8 A at VOUT1) to account for tolerances and ripple current. For this example, 130% of 8 A was chosen (10.4 A). The current sense resistor value is calculated with Equation 13 and the example (Equation 14).

Equation 13. LM25119 30126234.gif

where

  • VCS(TH) is the current limit threshold voltage (120 mV)
Equation 14. LM25119 30126235.gif

A value of 8 mΩ was chosen for RS. The sense resistor must be rated to handle the power dissipation at maximum input voltage when current flows through the free-wheel MOSFET for the majority of the PWM cycle. The maximum power dissipation of RS is calculated with Equation 15 and the example (Equation 16).

Equation 15. LM25119 30126236.gif
Equation 16. LM25119 30126237.gif

During output short condition, the worst-case peak inductor current is limited to Equation 17 and the example (Equation 18).

Equation 17. LM25119 30126238.gif

where

  • tON(MIN) is the minimum HO on-time which is nominally 100 ns
Equation 18. LM25119 30126239.gif

The chosen inductor must be evaluated for this condition, especially at elevated temperature where the saturation current rating of the inductor may drop significantly. At the maximum input voltage with a shorted output, the valley current must fall below VCS(TH) / RS before the high-side MOSFET is allowed to turn on.