SLUSD97 April   2018 LM25119Q

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Typical Application Circuit
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  High Voltage Start-Up Regulator
      2. 7.3.2  UVLO
      3. 7.3.3  Enable 2
      4. 7.3.4  Oscillator and Sync Capability
      5. 7.3.5  Error Amplifiers and PWM Comparators
      6. 7.3.6  Ramp Generator
      7. 7.3.7  Current Limit
      8. 7.3.8  Hiccup Mode Current Limiting
      9. 7.3.9  Soft Start
      10. 7.3.10 HO and LO Output Drivers
      11. 7.3.11 Maximum Duty Cycle
      12. 7.3.12 Thermal Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Diode Emulation
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Miscellaneous Functions
      2. 8.1.2 Interleaved Two-Phase Operation
      3. 8.1.3 Interleaved 4-Phase Operation
    2. 8.2 Typical Applications
      1. 8.2.1 Dual-output Design Example
        1. 8.2.1.1 Design Requirements
          1. 8.2.1.1.1 External Components
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1  Timing Resistor
          2. 8.2.1.2.2  Output Inductor
          3. 8.2.1.2.3  Current Sense Resistor
          4. 8.2.1.2.4  Ramp Resistor and Ramp Capacitor
          5. 8.2.1.2.5  Output Capacitors
          6. 8.2.1.2.6  Input Capacitors
          7. 8.2.1.2.7  VCC Capacitor
          8. 8.2.1.2.8  Bootstrap Capacitor
          9. 8.2.1.2.9  Soft Start Capacitor
          10. 8.2.1.2.10 Restart Capacitor
          11. 8.2.1.2.11 Output Voltage Divider
          12. 8.2.1.2.12 UVLO Divider
          13. 8.2.1.2.13 MOSFET Selection
          14. 8.2.1.2.14 MOSFET Snubber
          15. 8.2.1.2.15 Error Amplifier Compensation
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Two-Phase Design Example
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Switching Jitter Root Causes and Solutions
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Community Resources
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.1.2.12 UVLO Divider

The UVLO threshold is internally set to 1.25 V at the UVLO pin. The LM25119Q device is enabled when the system input voltage VIN causes the UVLO pin to exceed the threshold voltage of 1.25 V. When the UVLO pin voltage is below the threshold, the internal 20-μA current source is disabled. When the UVLO pin voltage exceeds the
1.25-V threshold, the 20-μA current source is enabled causing the UVLO pin voltage to increase, providing hysteresis. The values of RUV1 and RUV2 can be determined from Equation 34 and the example (Equation 35).

Equation 34. LM25119Q 30126254.gif
Equation 35. LM25119Q 30126255.gif

VHYS is the desired UVLO hysteresis at VIN, and VIN in the second equation is the desired UVLO release (turnon) voltage. For example, if it is desired for the LM25119Q device to be enabled when VIN reaches 5.6 V, and the desired hysteresis is 1.05 V, then RUV2 must be set to 52.5 kΩ and RUV1 must be set to 15.1 kΩ. For this application, RUV2 was selected to be 52.3 kΩ and RUV1was selected to be 15 kΩ. The LM25119Q device can be remotely shutdown by taking the UVLO pin below 0.4 V with an external open-collector or open-drain device. The outputs and the VCC regulator are disabled in shutdown mode. Capacitor CFT provides filtering for the divider. A value of 100 pF was chosen for CFT. The voltage at the UVLO pin must never exceed 15 V when using the external set-point divider. It may be necessary to clamp the UVLO pin at high input voltages.

LM25119Q uvlo_config_slusd97.gifFigure 17. UVLO Configuration