SNVSAF0B December   2015  – May 2016 LM25122-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Undervoltage Lockout (UVLO)
      2. 7.3.2  High Voltage VCC Regulator
      3. 7.3.3  Oscillator
      4. 7.3.4  Slope Compensation
      5. 7.3.5  Error Amplifier
      6. 7.3.6  PWM Comparator
      7. 7.3.7  Soft-Start
      8. 7.3.8  HO and LO Drivers
      9. 7.3.9  Bypass Operation (VOUT = VIN)
      10. 7.3.10 Cycle-by-Cycle Current Limit
      11. 7.3.11 Clock Synchronization
      12. 7.3.12 Maximum Duty Cycle
      13. 7.3.13 Thermal Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 MODE Control (Forced PWM Mode and Diode Emulation Mode)
      2. 7.4.2 MODE Control (Skip Cycle Mode and Pulse Skipping Mode)
      3. 7.4.3 Hiccup Mode Over-Load Protection
      4. 7.4.4 Slave Mode and SYNCOUT
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Feedback Compensation
      2. 8.1.2 Sub-Harmonic Oscillation
      3. 8.1.3 Interleaved Boost Configuration
      4. 8.1.4 DCR Sensing
      5. 8.1.5 Output Overvoltage Protection
      6. 8.1.6 SEPIC Converter Simplified Schematic
      7. 8.1.7 Non-Isolated Synchronous Flyback Converter Simplified Schematic
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Timing Resistor RT
        2. 8.2.2.2  UVLO Divider RUV2, RUV1
        3. 8.2.2.3  Input Inductor LIN
        4. 8.2.2.4  Current Sense Resistor RS
        5. 8.2.2.5  Current Sense Filter RCSFP, RCSFN, CCS
        6. 8.2.2.6  Slope Compensation Resistor RSLOPE
        7. 8.2.2.7  Output Capacitor COUT
        8. 8.2.2.8  Input Capacitor CIN
        9. 8.2.2.9  VIN Filter RVIN, CVIN
        10. 8.2.2.10 Bootstrap Capacitor CBST and Boost Diode DBST
        11. 8.2.2.11 VCC Capacitor CVCC
        12. 8.2.2.12 Output Voltage Divider RFB1, RFB2
        13. 8.2.2.13 Soft-Start Capacitor CSS
        14. 8.2.2.14 Restart Capacitor CRES
        15. 8.2.2.15 Low-Side Power Switch QL
        16. 8.2.2.16 High-Side Power Switch QH and Additional Parallel Schottky Diode
        17. 8.2.2.17 Snubber Components
        18. 8.2.2.18 Loop Compensation Components CCOMP, RCOMP, CHF
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Community Resources
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Layout

10.1 Layout Guidelines

In a boost regulator, the primary switching loop consists of the output capacitor and N-channel MOSFET power switches. Minimizing the area of this loop reduces the stray inductance and minimizes noise. Especially, placing high quality ceramic output capacitors as close to this loop earlier than bulk aluminum output capacitors minimizes output voltage ripple and ripple current of the aluminum capacitors.

In order to prevent a dv/dt induced turn-on of high-side switch, HO and SW should be connected to the gate and source of the high-side synchronous N-channel MOSFET switch through short and low inductance paths. In FPWM mode, the dv/dt induced turn-on can occur on the low-side switch. LO and PGND should be connected to the gate and source of the low-side N-channel MOSFET, through short and low inductance paths. All of the power ground connections should be connected to a single point. Also, all of the noise sensitive low power ground connections should be connected together near the AGND pin and a single connection should be made to the single point PGND. CSP and CSN are high impedance pins and noise sensitive. CSP and CSN traces should be routed together with kelvin connections to the current sense resistor as short as possible. If needed, place 100 pF ceramic filter capacitor as close to the device. MODE pin is also high impedance and noise sensitive. If an external pullup or pulldown resistor is used at MODE pin, the resistor should be placed as close the device. VCC, VIN and BST capacitor must be as physically close as possible to the device.

The LM25122 has an exposed thermal pad to aid power dissipation. Adding several vias under the exposed pad helps conduct heat away from the device. The junction to ambient thermal resistance varies with application. The most significant variables are the area of copper in the PC board, the number of vias under the exposed pad and the amount of forced air cooling. The integrity of the solder connection from the device exposed pad to the PC board is critical. Excessive voids greatly decrease the thermal dissipation capacity. The highest power dissipating components are the two power switches. Selecting N-channel MOSFET switches with exposed pads aids the power dissipation of these devices.

10.2 Layout Example

LM25122-Q1 lm5122_layout_snvs954.gif Figure 48. Power Path Layout