SNVSAP9A March   2017  – February 2018 LM25141-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  High Voltage Start-Up Regulator
      2. 7.3.2  VCC Regulator
      3. 7.3.3  Oscillator
      4. 7.3.4  Synchronization
      5. 7.3.5  Frequency Dithering (Spread Spectrum)
      6. 7.3.6  Enable
      7. 7.3.7  Power Good
      8. 7.3.8  Output Voltage
        1. 7.3.8.1 Minimum Output Voltage Adjustment
      9. 7.3.9  Current Sense
      10. 7.3.10 DCR Current Sensing
      11. 7.3.11 Error Amplifier and PWM Comparator
      12. 7.3.12 Slope Compensation
      13. 7.3.13 Hiccup Mode Current Limiting
      14. 7.3.14 Standby Mode
      15. 7.3.15 Soft Start
      16. 7.3.16 Diode Emulation
      17. 7.3.17 High- and Low-Side Drivers
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
        2. 8.2.2.2 Inductor Calculation
        3. 8.2.2.3 Current Sense Resistor
        4. 8.2.2.4 Output Capacitor
        5. 8.2.2.5 Input Filter
          1. 8.2.2.5.1 EMI Filter Design
          2. 8.2.2.5.2 MOSFET Selection
          3. 8.2.2.5.3 Driver Slew Rate Control
          4. 8.2.2.5.4 Frequency Dithering
        6. 8.2.2.6 Control Loop
          1. 8.2.2.6.1 Feedback Compensator
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Layout Procedure
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Custom Design With WEBENCH® Tools
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
        1. 11.2.1.1 PCB Layout Resources
        2. 11.2.1.2 Thermal Design Resources
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

TJ = –40°C to +125°C; typical values TJ = 25°C, VIN = 12 V, VCCX = 5 V, VOUT = 5 V, EN = 5 V, OSC = VDD, FSW = 2.2 MHz, no-load on the drive outputs (HO, HOL, LO, and LOL outputs), over operating free-air temperature range (unless otherwise noted)(1)(2)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
VIN SUPPLY VOLTAGE
ISHUTDOWN Shutdown mode current VIN = 8–18 V, EN = 0 V, VCCX = 0 V 10 12.5 µA
ISTANDBY Standby current EN = 5 V, FB = VDD, VOUT in regulation, no-load, not switching, DEMB = GND 35 45 µA
EN = 5 V, FB = 0 V, VOUT in regulation, no-load, not switching, VCCX = 5 V, DEMB = GND. 42 55
VCC REGULATOR
VCC(REG) VCC regulation voltage VIN = 6–18 V, 0–75 mA, VCCX = 0 V 4.75 5 5.25 V
VCC(UVLO) VCC undervoltage threshold VCC rising, VCCX = 0 V 3.25 3.4 3.55 V
VCC(HYST) VCC hysteresis voltage VCCX = 0 V 175 mV
ICC(LIM) VCC sourcing current limit VCCX = 0 V 85 125 mA
VDDA
VDDA(REG) Internal bias supply power VCCX = 0 V 4.75 5 5.25 V
VDDA(UVLO) VCC rising, VCCX = 0 V 3.1 3.2 3.3 V
VDDA(HYST) VCCX = 0 V 125 mV
RVDDA VCCX = 0 V 55 Ω
VCCX
VCCX(ON) VCC rising 4.1 4.3 4.4 V
VCCX(HYST) 80 mV
R(VCCX) VCCX = 5 V 2 Ω
OSCILLATOR SELECT THRESHOLDS
Oscillator select threshold 2.2 MHz (OSC pin) 2 V
Oscillator select threshold 440 kHz (OSC pin) 0.8 V
CURRENT LIMIT
V(CS) Current limit threshold ILSET = VDDA, measure from CS to VOUT 68 75 82 mV
tdly Current-sense delay to output 40 ns
Current-sense amplifier gain 11.4 12 12.6 V/V
ICS(BIAS) Amplifier input bias 10 nA
RES
I(RES) RES current source 20 µA
V(RES) RES threshold 1.2 V
Timer Timer hiccup-mode fault 512 cycles
RDS(ON) RES pulldown 4 Ω
OUTPUT VOLTAGE REGULATION
3.3 V VIN = 3.8–42 V 3.273 3.3 3.327 V
5 V VIN = 5.5–42 V 4.96 5 5.04 V
FEEDBACK
VOUT select threshold 3.3 V VDD – 0.3 V
Regulated feedback voltage 1.193 1.2 1.207 V
FB(LOWRES) Resistance to ground on FB for FB = 0 detection 500 Ω
FB(EXTRES) Thevenin equivalent resistance at FB for external regulation detection FB < 2 V 5 kΩ
TRANSCONDUCTANCE AMPLIFIER
Gm Gain Feedback to COMP 1010 1200 µS
Input bias current 15 nA
Transconductance amplifier source current COMP = 1 V, FB = 1 V 100 µA
Transconductance amplifier sink current COMP = 1 V, FB = 1.4 V 100 µA
POWER GOOD
PG(UV) PG undervoltage trip levels Falling with respect to the regulation voltage 90% 92% 94%
PG(OVP) PG overvoltage trip levels Rising with respect to the regulation voltage 108% 110% 112%
PG(HYST) 3.4%
PG(VOL) PG Open collector, Isink = 2 mA 0.4 V
PG(rdly) OV filter time VOUT rising 25 µs
PG(fdly) UV filter time VOUT falling 30 µs
HO GATE DRIVER
VOLH HO low-state output voltage IHO = 100 mA 0.05 V
VOHH HO high-state output voltage IHO = –100 mA, VOHH = VHB – VHO 0.07 V
trHO HO rise time (10% to 90%) CLOAD = 2700 pF 4 ns
tfHO HO fall time (90% to 10%) CLOAD = 2700 pF 3 ns
IOHH HO peak source current VHO = 0 V, SW = 0 V, HB = 5 V, VCCX = 5 V 3.25 Apk
IOLH HO peak sink current VCCX = 5 V 4.25 Apk
V(BOOT) UVLO HO falling 2.5 V
Hysteresis 110 mV
I(BOOT) Quiescent current 3 µA
LO GATE DRIVER
VOLL LO low-state output voltage ILO = 100 mA 0.05 V
VOHL LO high-state output voltage ILO = –100 mA, VOHL = VCC – VLO 0.07 V
trLO LO rise time (10% to 90%) CLOAD = 2700 pF 4 ns
tfLO LO fall time (90% to 10%) CLOAD = 2700 pF 3 ns
IOHL LO peak source current VCCX = 5 V 3.25 Apk
IOLL LO peak sink current VCCX = 5 V 4.25 Apk
ADAPTIVE DEAD TIME CONTROL
V(GS-DET) VGS detection threshold VGS falling, no-load 2.5 V
tdly1 HO off to LO on dead time 20 40 ns
tdly2 LO off to HO on dead time 20 38 ns
DIODE EMULATION
VIL DEMB input low threshold 0.8 V
VIH FPWM input high threshold 2 V
SW Zero cross threshold –5 mV
ENABLE INPUT
VIL Enable input low threshold VCCX = 0 V 0.8 V
VIH Enable input high threshold VCCX = 0 V 2 V
IIkg Leakage EN logic input only 1 µA
SYN INPUT (DEMB pin)
VIL DEMB input low threshold 0.8 V
VIH DEMB input high threshold 2 V
DEMB input low-frequency range 440 kHz 350 550 kHz
DEMB input high-frequency range 2.2 MHz 1800 2600 kHz
DITHER
IDITHER Dither source/sink current 20 µA
VDITHER Dither high threshold 1.26 V
Dither low threshold 1.14 V
SOFT START
ISS Soft-start current 16 22 28 µA
RDS(ON) Soft-start pulldown resistance 3 Ω
THERMAL
TSD Thermal shutdown 175 °C
Thermal shutdown hysteresis 15 °C
(1) All minimum and maximum limits are specified by correlating the electrical characteristics to process and temperature variations and applying statistical process control.
(2) The junction temperature (TJ in °C) is calculated from the ambient temperature (TA in °C) and power dissipation (PD in Watts) as follows: TJ = TA + (PD × RθJA) where RθJA (in °C/W) is the package thermal impedance provided in the Thermal Information section.