Based on the LM5143-Q1EVM-2100 design, Figure 12-2 shows a single-sided layout of a dual-output synchronous buck regulator. Each power stage is surrounded by a GND pad geometry to connect an EMI shield if needed. The design uses layer 2 of the PCB as a power-loop return path directly underneath the top layer to create a low-area switching power loop of approximately 2 mm². This loop area, and hence parasitic inductance, must be as small as possible to minimize EMI as well as switch-node voltage overshoot and ringing. Refer to the LM5143-Q1EVM-2100 Evaluation Module User's Guide for more detail.

Figure 12-2 PCB Top Layer

As shown in Figure 12-3, the high-frequency power loop current of one channel flows through MOSFETs Q2 and Q4, through the power ground plane on layer 2, and back to VIN through the 0603 ceramic capacitors C16 through C19. The currents flowing in opposing directions in the vertical loop configuration provide field self-cancellation, reducing parasitic inductance. Figure 12-4 shows a side view to illustrate the concept of creating a low-profile, self-canceling loop in a multilayer PCB structure. The layer-2 GND plane layer, shown in Figure 12-3, provides a tightly-coupled current return path directly under the MOSFETs to the source terminals of Q2.

Four 10-nF input capacitors with small 0402 or 0603 case size are placed in parallel very close to the drain of each high-side MOSFET. The low equivalent series inductance (ESL) and high self-resonant frequency (SRF) of the small footprint capacitors yield excellent high-frequency performance. The negative terminals of these capacitors are connected to the layer-2 GND plane with multiple 12-mil (0.3-mm) diameter vias, further minimizing parasitic loop inductance.

Additional steps used in this layout example include:

• Keep the SW connection from the power MOSFETs to the inductor (for each channel) at minimum copper area to reduce radiated EMI.
• Locate the controller close to the gate terminals of the MOSFETs such that the gate drive traces are routed short and direct.
• Create an analog ground plane near the controller for sensitive analog components. The analog ground plane for AGND and power ground planes for PGND1 and PGND2 must be connected at a single point directly under the IC – at the die attach pad (DAP).

Figure 12-3 Power Stage Component Layout

Note: See the Improve High-current DC/DC Regulator Performance for Free with Optimized Power Stage Layout application report for more detail.

Figure 12-4 PCB Stack-up Diagram With Low L1-L2 Intra-layer Spacing