SNVSC10 March   2022 LM25143

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Switching Characteristics
    7. 8.7 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Input Voltage Range (VIN)
      2. 9.3.2  High-Voltage Bias Supply Regulator (VCC, VCCX, VDDA)
      3. 9.3.3  Enable (EN1, EN2)
      4. 9.3.4  Power-Good Monitor (PG1, PG2)
      5. 9.3.5  Switching Frequency (RT)
      6. 9.3.6  Clock Synchronization (DEMB)
      7. 9.3.7  Synchronization Out (SYNCOUT)
      8. 9.3.8  Spread Spectrum Frequency Modulation (DITH)
      9. 9.3.9  Configurable Soft Start (SS1, SS2)
      10. 9.3.10 Output Voltage Setpoint (FB1, FB2)
      11. 9.3.11 Minimum Controllable On Time
      12. 9.3.12 Error Amplifier and PWM Comparator (FB1, FB2, COMP1, COMP2)
      13. 9.3.13 Slope Compensation
      14. 9.3.14 Inductor Current Sense (CS1, VOUT1, CS2, VOUT2)
        1. 9.3.14.1 Shunt Current Sensing
        2. 9.3.14.2 Inductor DCR Current Sensing
      15. 9.3.15 Hiccup Mode Current Limiting (RES)
      16. 9.3.16 High-Side and Low-Side Gate Drivers (HO1/2, LO1/2, HOL1/2, LOL1/2)
      17. 9.3.17 Output Configurations (MODE, FB2)
        1. 9.3.17.1 Independent Dual-Output Operation
        2. 9.3.17.2 Single-Output Interleaved Operation
        3. 9.3.17.3 Single-Output Multiphase Operation
    4. 9.4 Device Functional Modes
      1. 9.4.1 Standby Modes
      2. 9.4.2 Diode Emulation Mode
      3. 9.4.3 Thermal Shutdown
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Power Train Components
        1. 10.1.1.1 Buck Inductor
        2. 10.1.1.2 Output Capacitors
        3. 10.1.1.3 Input Capacitors
        4. 10.1.1.4 Power MOSFETs
        5. 10.1.1.5 EMI Filter
      2. 10.1.2 Error Amplifier and Compensation
    2. 10.2 Typical Applications
      1. 10.2.1 Design 1 – 5-V and 3.3-V Dual-Output Buck Regulator for Computing Applications
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 Custom Design With WEBENCH® Tools
          2. 10.2.1.2.2 Custom Design With Excel Quickstart Tool
          3. 10.2.1.2.3 Inductor Calculation
          4. 10.2.1.2.4 Current-Sense Resistance
          5. 10.2.1.2.5 Output Capacitors
          6. 10.2.1.2.6 Input Capacitors
          7. 10.2.1.2.7 Compensation Components
        3. 10.2.1.3 Application Curves
      2. 10.2.2 Design 2 – Two-Phase, 15-A, 2.1-MHz Single-Output Buck Regulator for Server Applications
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
        3. 10.2.2.3 Application Curves
      3. 10.2.3 Design 3 – Two-Phase, 50-A, 300-kHz Single-Output Buck Regulator for ASIC Power Applications
        1. 10.2.3.1 Design Requirements
        2. 10.2.3.2 Detailed Design Procedure
        3. 10.2.3.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Power Stage Layout
      2. 12.1.2 Gate-Drive Layout
      3. 12.1.3 PWM Controller Layout
      4. 12.1.4 Thermal Design and Layout
      5. 12.1.5 Ground Plane Design
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
      2. 13.1.2 Development Support
        1. 13.1.2.1 Custom Design With WEBENCH® Tools
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
        1. 13.2.1.1 PCB Layout Resources
        2. 13.2.1.2 Thermal Design Resources
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Support Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.5 Electrical Characteristics

Over the recommended operating junction temperature range of –40°C to 150°C (unless otherwise noted), typical values correspond to TJ = 25℃, VVIN = 12 V, VVCCX = 5 V, VVOUT1 = 3.3 V, VVOUT2 = 5 V, VEN1 = VEN2 = 5 V, RRT = 10 kΩ, FSW = 2.2 MHz, no load on the drive outputs (HO1, HOL1, LO1, LOL1, HO2, HOL2, LO2, and LOL2).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT VOLTAGE (VIN)
ISHUTDOWN Shutdown mode current VEN1 = VEN2 = 0 V 3.5 7 µA
ISTANDBY1 Standby current, channel 1 VEN1 = 5 V, VEN2 = 0 V, VVOUT1 = 3.3 V, in regulation, no load, not switching, DEMB = MODE = GND 24 µA
ISTANDBY2 Standby current, channel 2 VEN1 = 0 V, VEN2 = 5 V, VVOUT2 = 5 V, in regulation, no load, not switching, DEMB = MODE = GND 25 µA
ISTANDBY3 Standby current, channel 1, ultra-low IQ mode VEN1 = 5 V, VEN2 = 0 V, VVOUT1 = 3.3 V, in regulation, no load, not switching, DEMB = GND, RMODE = 10 kΩ to GND 16.5 µA
ISTANDBY4 Standby current, channel 2, ultra-low IQ mode VEN1 = 0 V, VEN2 = 5 V, VVOUT2 = 5 V,  in regulation, no load, not switching, DEMB = GND, RMODE = 10 kΩ to GND 21 µA
BIAS REGULATOR (VCC)
VVCC-REG VCC regulation voltage IVCC = 100 mA, VVCCX = 0 V 4.7 5 5.3 V
VCC-UVLO VCC UVLO rising threshold VVCC rising 3.2 3.3 3.4 V
VVCC-HYST VCC UVLO hysteresis 182 mV
IVCC-LIM VCC sourcing current limit 235 mA
ANALOG BIAS (VDDA)
VVDDA-REG VDDA regulation voltage 4.75 5 5.25 V
VVDDA-UVLO VDDA UVLO rising threshold VVCC rising, VVCCX = 0 V 3.1 3.2 3.3 V
VVDDA-HYST VDDA UVLO hysteresis VVCCX = 0 V 90 mV
RVDDA VDDA resistance VVCCX = 0 V 20 Ω
EXTERNAL BIAS (VCCX)
VVCCX-ON VCCX(ON) rising threshold 4.1 4.3 4.4 V
RVCCX VCCX resistance VVCCX = 5 V 1.2 Ω
VVCCX-HYST VCCX hysteresis voltage 130 mV
CURRENT LIMIT (CS1, CS2)
VCS1 Current limit threshold 1 Measured from CS1 to VOUT1 66 73 82 mV
VCS2 Current limit threshold 2 Measured from CS2 to VOUT2 66 73 82 mV
tCS-DELAY CS delay to output 40 ns
GCS CS amplifier gain 11.25 12 12.6 V/V
ICS-BIAS CS amplifier input bias current 15 nA
POWER GOOD (PG1, PG2)
PG1UV PG1 UV trip level Falling with respect to the regulation voltage 89.5% 92% 94%
PG2UV PG2 UV trip level Falling with respect to the regulation voltage 89.5% 92% 94%
PG2OV PG2 OV trip level Rising with respect to the regulation voltage 107.5% 110% 112.5%
PG2OV PG2 OV trip level Rising with respect to the regulation voltage 107.5% 110% 112.5%
PG1UV-HYST PG1 UV hysteresis Rising with respect to the regulation voltage 3.4%
PG1OV-HYST PG1 OV hysteresis Rising with respect to the regulation voltage 3.4%
PG2UV-HYST PG2 UV hysteresis Rising with respect to the regulation voltage 3.4%
PG2OV-HYST PG2 OV hysteresis Rising with respect to the regulation voltage 3.4%
VOL-PG1 PG1 voltage Open collector, IPG1 = 2 mA 0.4 V
VOL-PG2 PG2 voltage Open collector, IPG2 = 2 mA 0.4 V
tPG-RISE-DLY OV filter time VOUT rising 25 µs
tPG-FALL-DLY UV filter time VOUT falling 22 µs
HIGH-SIDE GATE DRIVER (HO1, HO2, HOL1, HOL2)
VHO-LOW HO low-state output voltage IHO = 100 mA 0.04 V
VHO-HIGH HO high-state output voltage IHO = –100 mA, VHO-HIGH = VHB – VHO 0.09 V
tHO-RISE HO rise time (10% to 90%) CLOAD = 2.7 nF 24 ns
tHO-FALL HO fall time (90% to 10%) CLOAD = 2.7 nF 24 ns
IHO-SRC HO peak source current VHO = VSW = 0 V, VHB = 5 V, VVCCX = 5 V 3.25 A
IHO-SINK HO peak sink current VVCCX = 5 V 4.25 A
VBT-UV BOOT UVLO VVCC falling 2.45 V
VBT-UV-HYS BOOT UVLO hysteresis 113 mV
IBOOT BOOT quiescent current 1.25 µA
LOW-SIDE GATE DRIVER (LO1, LO2, LOL1, LOL2)
VLO-LOW LO low-state output voltage ILO = 100 mA 0.04 V
VLO-HIGH LO high-state output voltage ILO = –100 mA 0.07 V
tLO-RISE LO rise time (10% to 90%) CLOAD = 2.7 nF 4 ns
tLO-FALL LO fall time (90% to 10%) CLOAD = 2.7 nF 3 ns
ILO-SOURCE LO peak source current VHO = VSW = 0 V, VHB = 5 V, VVCCX = 5 V 3.25 A
ILO-SINK LO peak sink current VVCCX = 5 V 4.25 A
RESTART (RES)
IRES-SRC RES current source 20 µA
VRES-TH RES threshold 1.2 V
HICCYCLES HICCUP mode fault 512 cycles
RRES-PD RES pulldown resistance 5.7 Ω
OUTPUT VOLTAGE SETPOINT (VOUT1, VOUT2)
VOUT33 3.3-V output voltage setpoint FB = VDDA, VIN = 3.5 V to 65 V 3.267 3.3 3.335 V
VOUT50 5-V output voltage setpoint FB = AGND, VIN = 5.5 V to 65 V 4.95 5 5.05 V
FEEDBACK (FB1, FB2)
VFB-3V3-SEL VOUT select threshold 3.3-V output 4.6 V
RFB-5V Resistance FB to AGND for 5-V output VMODE = 0 V or RMODE = 10 kΩ 500 Ω
RFB-EXTRES Thevenin equivelent resistance VMODE = 0 V or RMODE = 10 kΩ, VFB < 2 V 5 kΩ
VFB2-LOW Primary mode select logic level low MODE = VDDA 0.8 V
VFB2-HIGH Primary mode select logic level high MODE = VDDA 2 V
VFB1-LOW Diode emulation logic level low in secondary mode MODE = FB2 = VDDA 0.8 V
VFB1-HIGH FPWM logic level high in secondary mode MODE = FB2 = VDDA 2 V
VFB-REG Regulated feedback voltage TJ = –40°C to 125°C 0.594 0.6 0.606 V
ERROR AMPLIFIER (COMP1, COMP2)
gm1 EA transconductance FB to COMP, RMODE < 5 kΩ to AGND 1020 1200 µs
gm2 EA transconductance, ultra-low IQ mode MODE = GND, RMODE = 10 kΩ            65 µs
IFB Error amplifier input bias current 30 nA
VCOMP-CLMP COMP clamp voltage VFB = 0 V 3.3 V
ICOMP-SECOND COMP leakage, secondary mode VCOMP = 1 V, MODE = FB2 = VDDA 10 nA
ICOMP-INTLV COMP2 leakage, interleaved mode VCOMP = 1 V, MODE = VDDA, VFB2 = 0 V 10 nA
ICOMP-SRC1 EA source current VCOMP = 1 V, VFB = 0.4 V, VMODE = 0 V 190 µA
ICOMP-SINK1 EA sink current VCOMP = 1 V, VFB = 0.8 V, VMODE = 0 V 160 µA
ICOMP-SRC2 EA source current, ultra-low IQ mode VCOMP = 1 V, VFB = 0.4 V,
RMODE = 10 kΩ to AGND		 10 µA
ICOMP-SINK2 EA sink current, ultra-low IQ mode VCOMP = 1 V, VFB = 0.8 V,
RMODE = 10 kΩ to AGND		 12 µA
VSS-OFFSET EA SS offset with VFB = 0 V Raise VSS until VCOMP > 300 mV 36 mV
ADAPTIVE DEADTIME CONTROL
VGS-DET VGS detection threshold VGS falling, no load 2.1 V
tDEAD1 HO off to LO on dead time 22 ns
tDEAD2 LO off to HO on dead time 20 ns
DIODE EMULATION (DEMB)
VDEMB-LOW DEMB input low threshold 0.8 V
VDEMB_Rising DEMB input high threshold 2 V
VZC-SW Zero-cross threshold VDEMB = 0 V –7 mV
VZC-SS Zero-cross threshold soft start DEMB = VDDA,
50 SW cycles after first HO pulse		 –6.1 mV
VZC-DIS Zero-cross threshold disabled DEMB = VDDA,
1000 SW cycles after first HO pulse		 210 mV
ENABLE (EN1, EN2)
VEN-LOW EN1/2 low threshold VVCCX = 0 V 0.8 V
VEN-HIGH-TH EN1/2 high threshold VVCCX = 0 V 2 V
IEN-LEAK EN1/2 leakage currernt EN1, EN2 logic inputs only 0.05 µA
SWITCHING FREQUENCY (RT)
VRT RT regulation voltage 10 kΩ < RRT < 220 kΩ 0.8 V
MODE
RMODE-HIGH Resistance to AGND for ultra-low IQ 5  kΩ
RMODE-LOW Resistance to AGND for normal IQ 0.5 kΩ
VMODE-LOW Non-interleaved mode input low threshold 0.8 V
VMODE-HIGH Interleaved mode input high threshold 2 V
SYNCHRONIZATION INPUT (SYNCIN)
VDEMB-LOW DEMB input low threshold 0.8 V
VDEMB-HIGH DEMB input high threshold 2 V
tSYNC-MIN DEMB minimum pulse width VMODE = 0 V or RMODE = 10 kΩ 20 250 ns
FSYNCIN External SYNC frequency range VIN = 8 V to 18 V, % of the nominal frequency set by RRT –20% 20%
tSYNCIN-HO1 Delay from DEMB rising to HO1 rising edge 120 ns
tSYNCIN-SECOND Delay from DEMB falling edge to HO2 rising edge Secondary mode, MODE = FB2 = VDDA 100 ns
tDEMB-FILTER Delay from DEMB low to diode emulation enable VMODE = 0 V or RMODE = 10 kΩ 15 50 µs
tAWAKE-FILTER Maximum SYNC period to maintain standby state VEN1 = VEN2 = 0 V 27 µs
SYNCHRONIZATION OUTPUT (SYNCOUT)
VSYNCOUT-LO SYNCOUT low-state voltage ISYNCOUT = 16 mA 0.8 V
FSYNCOUT SYNCOUT frequency MODE = FB2 = VDDA 0 Hz
tSYNCOUT1 Delay from HO2 rising edge to SYNCOUT rising edge VDEMB = 0 V, TS = 1/FSW, FSW set by RRT = 220 kΩ 2.5 µs
tSYNCOUT2 Delay from HO2 rising edge to SYNCOUT falling edge VDEMB = 0 V, TS = 1/FSW, FSW set by RRT = 220 kΩ 7.5 µs
DITHER (DITH)
IDITH Dither source/sink current 21 µA
VDITH-HIGH Dither high-level threshold 1.25 V
VDITH-LOW Dither low-level threshold 1.15 V
SOFT START (SS1, SS2)
ISS Soft-start current VMODE = 0 V 16 21 28 µA
RSS-PD Soft-start pulldown resistance VMODE = 0 V 3 Ω
VSS-FB SS to FB clamp voltage VCS – VVOUT > 73 mV 130 mV
ISS-SECOND SS leakage, secondary mode VSS = 0.8 V, MODE = FB2 = VDDA 30 nA
ISS-INTLV SS2 leakage, interleaved mode VSS = 0.8 V, MODE = VDDA, VFB2 = 0 V 21 nA
THERMAL SHUTDOWN
TSHD Thermal shutdown 175 °C
TSHD-HYS Thermal shutdown hysteresis 15 °C