SNVSCT9 October   2024 LM251772

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Handling Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Buck-Boost Control Scheme
        1. 8.3.1.1 Buck Mode
        2. 8.3.1.2 Boost Mode
        3. 8.3.1.3 Buck-Boost Mode
      2. 8.3.2  Power Save Mode
      3. 8.3.3  Reference System
        1. 8.3.3.1 VIO LDO and nRST-PIN
      4. 8.3.4  Supply Voltage Selection – VSMART Switch and Selection Logic
      5. 8.3.5  Enable and Undervoltage Lockout
        1. 8.3.5.1 UVLO
      6. 8.3.6  Internal VCC Regulators
        1. 8.3.6.1 VCC1 Regulator
        2. 8.3.6.2 VCC2 Regulator
      7. 8.3.7  Error Amplifier and Control
        1. 8.3.7.1 Output Voltage Regulation
        2. 8.3.7.2 Output Voltage Feedback
        3. 8.3.7.3 Voltage Regulation Loop
        4. 8.3.7.4 Dynamic Voltage Scaling
      8. 8.3.8  Output Voltage Discharge
      9. 8.3.9  Peak Current Sensor
      10. 8.3.10 Short Circuit - Hiccup Protection
      11. 8.3.11 Current Monitor/Limiter
        1. 8.3.11.1 Overview
        2. 8.3.11.2 Output Current Limitation
        3. 8.3.11.3 Output Current Monitor
      12. 8.3.12 Oscillator Frequency Selection
      13. 8.3.13 Frequency Synchronization
      14. 8.3.14 Output Voltage Tracking
        1. 8.3.14.1 Analog Voltage Tracking
        2. 8.3.14.2 Digital Voltage Tracking
      15. 8.3.15 Slope Compensation
      16. 8.3.16 Configurable Soft Start
      17. 8.3.17 Drive Pin
      18. 8.3.18 Dual Random Spread Spectrum – DRSS
      19. 8.3.19 Gate Driver
      20. 8.3.20 Cable Drop Compensation (CDC)
      21. 8.3.21 CFG-pin and R2D Interface
      22. 8.3.22 Advanced Monitoring Features
        1. 8.3.22.1  Overview
        2. 8.3.22.2  BUSY
        3. 8.3.22.3  OFF
        4. 8.3.22.4  VOUT
        5. 8.3.22.5  IOUT
        6. 8.3.22.6  INPUT
        7. 8.3.22.7  TEMPERATURE
        8. 8.3.22.8  CML
        9. 8.3.22.9  OTHER
        10. 8.3.22.10 ILIM_OP
        11. 8.3.22.11 nFLT/nINT Pin Output
        12. 8.3.22.12 Status Byte
      23. 8.3.23 Protection Features
        1. 8.3.23.1  Thermal Shutdown (TSD)
        2. 8.3.23.2  Over Current Protection
        3. 8.3.23.3  Output Over Voltage Protection 1 (OVP1)
        4. 8.3.23.4  Output Over Voltage Protection 2 (OVP2)
        5. 8.3.23.5  Input Voltage Protection (IVP)
        6. 8.3.23.6  Input Voltage Regulation (IVR)
        7. 8.3.23.7  Power Good
        8. 8.3.23.8  Boot-Strap Under Voltage Protection
        9. 8.3.23.9  Boot-strap Over Voltage Clamp
        10. 8.3.23.10 CRC - CHECK
    4. 8.4 Device Functional Modes
      1. 8.4.1 Overview
      2. 8.4.2 Logic State Description
    5. 8.5 Programming
      1. 8.5.1 I2C Bus Operation
      2. 8.5.2 Clock Stretching
      3. 8.5.3 Data Transfer Formats
      4. 8.5.4 Single READ from a Defined Register Address
      5. 8.5.5 Sequential READ Starting from a Defined Register Address
      6. 8.5.6 Single WRITE to a Defined Register Address
      7. 8.5.7 Sequential WRITE Starting at a Defined Register Address
  10. 9 LM251772 Registers
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1  Custom Design with WEBENCH Tools
        2. 10.2.2.2  Frequency
        3. 10.2.2.3  Feedback Divider
        4. 10.2.2.4  Inductor and Current Sense Resistor Selection
        5. 10.2.2.5  Output Capacitor
        6. 10.2.2.6  Input Capacitor
        7. 10.2.2.7  Slope Compensation
        8. 10.2.2.8  UVLO Divider
        9. 10.2.2.9  Soft-Start Capacitor
        10. 10.2.2.10 MOSFETs QH1 and QL1
        11. 10.2.2.11 MOSFETs QH2 and QL2
        12. 10.2.2.12 Loop Compensation
        13. 10.2.2.13 External Component Selection
      3. 10.2.3 Application Curves
    3. 10.3 Wireless Charging Supply
    4. 10.4 USB-PD Source with Power Path
    5. 10.5 Parallel (Multiphase) Operation
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.21 CFG-pin and R2D Interface

The LM251772 has four resistor to digital configuration pins (R2D), where the CFG1 is used to control to the ADDR/SLOPE -pin. The channels CFG3 and CFG4 are multiplexed with the SDA/SCL pins, and can only be used when I2C function is disabled.

The resistor value on the CFG pins is read and latched during the power-up sequence of the device. The selection cannot be changed until the voltage on the nRST pin is toggled or VCC2 voltage drops below the VVCC2T-(UVLO) threshold. The Table 8-4 shows the possible device configurations versus the different resistor values on the CFG pins.

Table 8-4 ADDR/Slope Pin (R2D-CH1) Configuration Overview
# R(CFG) / kΩ I2C/ADDR Slope Compensation (m(SC))
1 GND I2C ENABLED Address 0x6A Default NVM setting 0.875
2 0.511 I2C DISABLED 0.25
3 1.15 0.375
4 1.9 0.5
5 2.7 0.625
6 3.8 0.75
7 5.1 0.875
8 6.5 1
9 8.3 1.5
10 10.5 2
11 13.3 2.5
12 16.2 3
13 20.5 3.5
14 24.9 4
15 30.1 4.5
16 VCC2 I2C ENABLED Address 0x6B Default NVM setting 0.875
Table 8-5 CFG2 Pin (R2D-CH2) Configuration Overview
# R(CFG) / kΩ EN_SYNC_OUT SYNC_IN_FALLING FORCE_BIAS UNUSED
1 0 DISABLED DISABLED DISABLED RESERVED
2 0.511 ENABLED
3 1.15 DISABLED ENABLED
4 1.9 ENABLED
5 2.7 DISABLED DISABLED ENABLED
6 3.8 ENABLED
7 5.1 DISABLED ENABLED
8 6.5 ENABLED
9 8.3 DISABLED DISABLED DISABLED
10 10.5 ENABLED
11 13.3 DISABLED ENABLED
12 16.2 ENABLED
13 20.5 DISABLED DISABLED ENABLED
14 24.9 ENABLED
15 30.1 DISABLED ENABLED
16 36.5 ENABLED
Table 8-6 CFG3 Pin (R2D-CH3) Configuration Overview
# R(CFG) / kΩ EN_VCC1 INC_INDUCT_DE-RATE μSLEEP SCALE_DT
1 0 DISABLED DISABLED (30%) DISABLED DISABLE
2 0.511 ENABLED
3 1.15 DISABLED ENABLED (40%)
4 1.9 ENABLED
5 2.7 DISABLED DISABLED (30%) ENABLED
6 3.8 ENABLED
7 5.1 DISABLED ENABLED (40%)
8 6.5 ENABLED
9 8.3 DISABLED DISABLED (30%) DISABLED ENABLED
10 10.5 ENABLED
11 13.3 DISABLED ENABLED (40%)
12 16.2 ENABLED
13 20.5 DISABLED DISABLED (30%) ENABLED
14 24.9 ENABLED
15 30.1 DISABLED ENABLED (40%)
16 36.5 ENABLED
Table 8-7 CFG4 Pin (R2D-CH4) Configuration Overview
# R(CFG) / kΩ DRSS SCP – Hiccup Mode Negative Current Limit Current Limit
1 0 DISABLED DISABLED DISABLED DISABLE
2 0.511 ENABLED
3 1.15 DISABLED ENABLED
4 1.9 ENABLED
5 2.7 DISABLED DISABLED ENABLED
6 3.8 ENABLED
7 5.1 DISABLED ENABLED
8 6.5 ENABLED
9 8.3 DISABLED DISABLED DISABLED ENABLED
10 10.5 ENABLED
11 13.3 DISABLED ENABLED
12 16.2 ENABLED
13 20.5 DISABLED DISABLED ENABLED
14 24.9 ENABLED
15 30.1 DISABLED ENABLED
16 36.5 ENABLED