7.3.1 Sleep Mode

In light load conditions, the LM26001 automatically switches into sleep mode for improved efficiency. As loading decreases, the voltage at FB increases and the COMP voltage decreases. When the COMP voltage reaches the 0.6-V (typical) clamp threshold, and the FB voltage rises 1% above nominal, sleep mode is enabled and switching stops. The regulator remains in sleep mode until the FB voltage falls to the reset threshold, at which point switching resumes. This 1% FB window limits the corresponding output ripple to approximately 1% of nominal output voltage. The sleep cycle will repeat until load current is increased. Figure 15 shows typical switching and output voltage waveforms in sleep mode.

Figure 15. Sleep Mode Waveforms 25-mA Load, Vin = 12 V

In sleep mode, quiescent current is reduced to less than 40 µA when not switching. The DC sleep mode threshold can be calculated according to the equation below:

Equation 1.

Where Imin = Ilim/16 (2.5A/16 typically) and D = duty cycle, defined as (Vout + Vdiode)/Vin.

When load current increases above this limit, the LM26001 is forced back into normal PWM operation. The sleep mode threshold varies with frequency, inductance, and duty cycle as shown in Figure 16.

Figure 16. Sleep Mode Threshold vs Vin Vout = 3.3 V

Below the sleep threshold, decreasing load current results in longer sleep cycles, which can be quantified as shown below:

Where Dwake is the percentage of time awake when the load current is below the sleep threshold.

Sleep mode combined with low IQ operation minimizes the input supply current. Input supply current in sleep mode can be calculated based on the wake duty cycle, as shown below:

Where I_QG is the gate drive current, calculated as:

I_QG = (4.6 x 10^-9) x f_SW

And Io is the sum of Iload, Ibias, and current through the feedback resistors.

Because this calculation applies only to sleep mode, use the I_{q_Sleep_VB} and I_{BIAS_SLEEP} values from the Electrical Characteristics. If VBIAS is connected to ground, use the same equation with Ibias equal to zero and I_{q_Sleep_VDD}.

7.3.2 FPWM

Pulling the FPWM pin high disables sleep mode and forces the LM26001 to always operate in PWM mode. Light load efficiency is reduced in PWM mode, but switching frequency remains stable. The FPWM pin can be connected to the VDD pin to pull it high. In FPWM mode, under light load conditions, the regulator operates in discontinuous conduction mode (DCM) . In discontinuous conduction mode, current through the inductor starts at zero and ramps up to its peak, then ramps down to zero again. Until the next cycle, the inductor current remains at zero. At nominal load currents, in FPWM mode, the device operates in continuous conduction mode, where positive current always flows in the inductor. Typical discontinuous operation waveforms are shown in Figure 17.

Figure 17. Discontinuous Mode Waveforms 75-mA Load, Vin = 12 V

At very light load, in FPWM mode, the LM26001 may enter sleep mode. This is to prevent an over-voltage condition from occurring. However, the FPWM sleep threshold is much lower than in normal operation.

7.3.3 Enable

The LM26001 provides a shutdown function via the EN pin to disable the device when the output voltage does not need to be maintained. EN is an analog level input with typically 120 mV of hysteresis. The device is active when the EN pin is above 1.2 V (typical) and in shutdown mode when EN is below this threshold. When EN goes high, the internal VDD regulator turns on and charges the VDD capacitor. When VDD reaches 3.9 V (typical), the soft-start pin begins to source current. In shutdown mode, the VDD regulator shuts down and total quiescent current is reduced to 10 µA (typical). Because the EN pin sources 4.5 µA (typical) of pull-up current, this pin can be left open for always-on operation. When open, EN will be pulled up to VIN.

If EN is connected to VIN, it must be connected through a 10 kΩ resistor to limit noise spikes. EN can also be driven externally with a maximum voltage of 38V or VIN + 15V, whichever is lower.

7.3.4 Soft-Start

The soft-start feature provides a controlled output voltage ramp up at startup. This reduces inrush current and eliminates output overshoot at turn-on. The soft-start pin, SS, must be connected to GND through a capacitor. At power-on, enable, or UVLO recovery, an internal 2.2 µA (typical) current charges the soft-start capacitor. During soft-start, the error amplifier output voltage is controlled by both the soft-start voltage and the feedback loop. As the SS pin voltage ramps up, the duty cycle increases proportional to the soft-start ramp, causing the output voltage to ramp up. The rate at which the duty cycle increases depends on the capacitance of the soft-start capacitor. The higher the capacitance, the slower the output voltage ramps up. The soft-start capacitor value can be calculated with the following equation:

Equation 4.

Where tss is the desired soft-start time and Iss is the soft-start source current. During soft-start, current limit and synchronization remain in effect, while sleep mode and frequency foldback are disabled. Soft-start mode ends when the SS pin voltage reaches 1.23 V typical. At this point, output voltage control is transferred to the FB pin and the SS pin is discharged.

7.3.5 Current Limit

The peak current limit is set internally by directly measuring peak inductor current through the internal switch. To ensure accurate current sensing, VIN should be bypassed with a minimum 1-µF ceramic capacitor placed directly at the pin.

When the inductor current reaches the current limit threshold, the internal FET turns off immediately allowing inductor current to ramp down until the next cycle. This reduction in duty cycle corresponds to a reduction in output voltage.

The current limit comparator is disabled for less than 100 ns at the leading edge for increased immunity to switching noise.

Because the current limit monitors peak inductor current, the DC load current limit threshold varies with inductance and frequency. Assuming a minimum current limit of 1.85A, maximum load current can be calculated as follows:

Equation 5.

Where Iripple is the peak-to-peak inductor ripple current, calculated as shown below:

Equation 6.

To find the worst case (lowest) current limit threshold, use the maximum input voltage and minimum current limit specification.

During high over-current conditions, such as output short circuit, the LM26001 employs frequency foldback as a second level of protection. If the feedback voltage falls below the short circuit threshold of 0.9 V, operating frequency is reduced, thereby reducing average switch current. This is especially helpful in short circuit conditions, when inductor current can rise very high during the minimum on-time. Frequency reduction begins at 20% below the nominal frequency setting. The minimum operating frequency in foldback mode is 71 kHz typical.

If the FB voltage falls below the frequency foldback threshold during frequency synchronized operation, the SYNC function is disabled. Operating frequency versus FB voltage in short circuit conditions is shown in the Typical Characteristics section.

Under conditions where the on time is close to minimum (less than 200 nsec typically), such as high input voltage and high switching frequency, the current limit may not function properly. This is because the current limit circuit cannot reduce the on-time below minimum which prevents entry into frequency foldback mode. There are two ways to ensure proper current limit and foldback operation under high input voltage conditions. First, the operating frequency can be reduced to increase the nominal on time. Second, the inductor value can be increased to slow the current ramp and reduce the peak over-current.

7.3.6 Frequency Adjustment and Synchronization

The switching frequency of the LM26001 can be adjusted between 150 kHz and 500 kHz using a single external resistor. This resistor is connected from the FREQ pin to ground as shown in the typical application. The resistor value can be calculated with the following empirically derived equation:

Figure 18. Switching Frequency vs R_FREQ

The switching frequency can also be synchronized to an external clock signal using the SYNC pin. The SYNC pin allows the operating frequency to be varied above and below the nominal frequency setting. The adjustment range is from 30% above nominal to 20% below nominal. External synchronization requires a 1.2V (typical) peak signal level at the SYNC pin. The FREQ resistor must always be connected to initialize the nominal operating frequency. The operating frequency is synchronized to the falling edge of the SYNC input. When SYNC goes low, the high-side switch turns on. This allows any duty cycle to be used for the sync signal when synchronizing to a frequency higher than nominal. When synchronizing to a lower frequency, however, there is a minimum duty cycle requirement for the SYNC signal, given in the equation below:

Equation 8.

Where fnom is the nominal switching frequency set by the FREQ resistor, and fsync is a square wave. If the SYNC pin is not used, it must be pulled low for normal operation. A 10 kΩ pull-down resistor is recommended to protect against a missing sync signal. Although the LM26001 is designed to operate at up to 500 kHz, maximum load current may be limited at higher frequencies due to increased temperature rise. See the Thermal Considerations and TSD section.

7.3.7 VBIAS

The VBIAS pin is used to bypass the internal regulator which provides the bias voltage to the LM26001. When the VBIAS pin is connected to a voltage greater than 3 V, the internal regulator automatically switches over to the VBIAS input. This reduces the current into VIN (Iq) and increases system efficiency. Using the VBIAS pin has the added benefit of reducing power dissipation within the device.

For most applications where 3 V < Vout < 10V, VBIAS can be connected to Vout. If not used, VBIAS should be tied to GND.

If VBIAS drops below 2.9 V (typical), the device automatically switches over to supply the internal bias voltage from Vin.

7.3.8 Low VIN Operation and UVLO

The LM26001 is designed to remain operational during short line transients when input voltage may drop as low as 3.0 V. Minimum nominal operating input voltage is 4.0 V. Below this voltage, switch R_DS(ON) increases, due to the lower gate drive voltage from VDD. The minimum voltage required at VDD is approximately 3.5 V for normal operation within specification.

VDD can also be used as a pull-up voltage for functions such as PGOOD and FPWM. Note that if VDD is used externally, the pin is not recommended for loads greater than 1 mA.

If the input voltage approaches the nominal output voltage, the duty cycle is maximized to hold up the output voltage. In this mode of operation, once the duty cycle reaches its maximum, the LM26001 can skip a maximum of seven off pulses, effectively increasing the duty cycle and thus minimizing the dropout from input to output. Typical off-pulse skipping waveforms are shown in Figure 19.

Figure 19. Off-pulse Skipping Waveforms Vin = 3.5 V, Vnom = 3.3 V, fnom = 305 kHz

UVLO is sensed at both VIN and VDD, and is activated when either voltage falls below 2.9 V (typical). Although VDD is typically less than 200 mV below VIN, it will not discharge through VIN. Therefore when the VIN voltage drops rapidly, VDD may remain high, especially in sleep mode. For fast line voltage transients, using a larger capacitor at the VDD pin can help to hold off a UVLO shutdown by extending the VDD discharge time. By holding up VDD, a larger cap can also reduce the R_DS(ON) (and dropout voltage) in low VIN conditions. Alternately, under heavy loading the VDD voltage can fall several hundred mV below VIN. In this case, UVLO may be triggered by VDD even though the VIN voltage is above the UVLO threshold.

When UVLO is activated the LM26001 enters a standby state in which VDD remains charged. As input voltage and VDD voltage rise above 3.9 V (typical) the device will restart from softstart mode.

7.3.9 PGOOD

A power good pin, PGOOD, is available to monitor the output voltage status. The pin is internally connected to an open-drain MOSFET, which remains open while the output voltage is within operating range. PGOOD goes low (low impedance to ground) when the output falls below 85% of nominal or EN is pulled low. When the output voltage returns to within 92% of nominal, as measured at the FB pin, PGOOD returns to a high state. For improved noise immunity, there is a 5 µs delay between the PGOOD threshold and the PGOOD pin going low.