SNVS615K January   2010  – February 2018 LM27402

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Typical Application Circuit
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Performance Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Wide Input Voltage Range
      2. 7.3.2  UVLO
      3. 7.3.3  Precision Enable
      4. 7.3.4  Soft-Start and Voltage Tracking
      5. 7.3.5  Output Voltage Setpoint and Accuracy
      6. 7.3.6  Voltage-Mode Control
      7. 7.3.7  Power Good
      8. 7.3.8  Inductor-DCR-Based Overcurrent Protection
      9. 7.3.9  Current Sensing
      10. 7.3.10 Power MOSFET Gate Drivers
      11. 7.3.11 Pre-Bias Start-up
    4. 7.4 Device Functional Modes
      1. 7.4.1 Fault Conditions
        1. 7.4.1.1 Thermal Protection
        2. 7.4.1.2 Current Limit
        3. 7.4.1.3 Negative Current Limit
        4. 7.4.1.4 Undervoltage Threshold (UVT)
        5. 7.4.1.5 Overvoltage Threshold (OVT)
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1  Converter Design
      2. 8.1.2  Inductor Selection (L)
      3. 8.1.3  Output Capacitor Selection (COUT)
      4. 8.1.4  Input Capacitor Selection (CIN)
      5. 8.1.5  Using Precision Enable
      6. 8.1.6  Setting the Soft-Start Time
      7. 8.1.7  Tracking
      8. 8.1.8  Setting the Switching Frequency
      9. 8.1.9  Setting the Current Limit Threshold
      10. 8.1.10 Control Loop Compensation
      11. 8.1.11 MOSFET Gate Drivers
      12. 8.1.12 Power Loss and Efficiency Calculations
        1. 8.1.12.1 Power MOSFETs
        2. 8.1.12.2 High-Side Power MOSFET
        3. 8.1.12.3 Low-Side Power MOSFET
        4. 8.1.12.4 Gate-Charge Loss
        5. 8.1.12.5 Input and Output Capacitor ESR Losses
        6. 8.1.12.6 Inductor Losses
        7. 8.1.12.7 Controller Losses
        8. 8.1.12.8 Overall Efficiency
    2. 8.2 Typical Applications
      1. 8.2.1 Example Circuit 1
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Custom Design With WEBENCH® Tools
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Example Circuit 2
      3. 8.2.3 Example Circuit 3
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Power Stage Layout
      2. 10.1.2 Gate Drive Layout
      3. 10.1.3 Controller Layout
      4. 10.1.4 Thermal Design and Layout
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Development Support
        1. 11.1.2.1 Custom Design With WEBENCH® Tools
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.1 Wide Input Voltage Range

The LM27402 operating input voltage range is from 3 V to 20 V. The device is intended for POL conversions from 3.3-V, 5-V, and 12-V unregulated, semiregulated and fully regulated supply rails. It is also suitable for connection to intermediate bus converters with output rails centered at 12 V and 9.6 V (derived from 4:1 and 5:1 primary-secondary transformer step-downs in nonregulated full-bridge converter topologies) and voltage levels intrinsic to a wide variety of battery chemistries.

The LM27402 uses an internal LDO subregulator to provide a 4.5-V bias rail for the gate drive and control circuits (assuming the input voltage is higher than 4.5 V plus the necessary subregulator dropout specification). Naturally, it can be more favorable to connect VDD directly to the input during low input voltage operation
(VVIN < 5.5 V). In summary, connecting VDD to VIN during low input voltage operation provides a greater gate drive voltage level and thus an inherent efficiency benefit. However, by virtue of the low subregulator dropout voltage, this VDD to VIN connection is not mandatory, thus enabling input ranges from 3 V up to 20 V.

In general, the subregulator is rated to drive the two internal gate driver stages in addition to the quiescent current associated with the operation of the LM27402. VDD and VIN pins of the LM27402 can be tied together if the input voltage is ensured not to exceed 5.5 V (absolute maximum 6 V). This connection bypasses the internal LDO bias regulator and eliminates the LDO dropout voltage and power dissipation. An RC filter from the input rail to the VIN pin, for example 2.2 Ω and 1 µF, presents supplementary filtering at the VIN pin. Low gate threshold voltage MOSFETs are recommended for this configuration.