SNVS896B August   2013  – November 2014 LM27403

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (Continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Handling Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Input Range: VIN
      2. 8.3.2  Output Voltage: FB Voltage and Accuracy
      3. 8.3.3  Input and Bias Rail Voltages: VIN and VDD
      4. 8.3.4  Precision Enable: UVLO/EN
      5. 8.3.5  Switching Frequency
        1. 8.3.5.1 Frequency Adjust: FADJ
        2. 8.3.5.2 Clock Synchronization: SYNC
      6. 8.3.6  Temperature Sensing: D+ and D-
      7. 8.3.7  Thermal Shutdown: OTP
      8. 8.3.8  Inductor-DCR-Based Overcurrent Protection
      9. 8.3.9  Current Sensing: CS+ and CS-
      10. 8.3.10 Current Limit Handling
      11. 8.3.11 Soft-Start: SS/TRACK
        1. 8.3.11.1 Tracking
      12. 8.3.12 Monotonic Startup
      13. 8.3.13 Prebias Startup
      14. 8.3.14 Voltage-Mode Control
      15. 8.3.15 Output Voltage Remote Sense: RS
      16. 8.3.16 Power Good: PGOOD
      17. 8.3.17 Gate Drivers: LG and HG
      18. 8.3.18 Sink and Source Capability
    4. 8.4 Device Functional Modes
      1. 8.4.1 Fault Conditions
        1. 8.4.1.1 Thermal Shutdown
        2. 8.4.1.2 Current Limit and Short Circuit Operation (Positive Overcurrent)
        3. 8.4.1.3 Negative Current Limit
        4. 8.4.1.4 Undervoltage Threshold (UVT)
        5. 8.4.1.5 Overvoltage Threshold (OVT)
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Design and Implementation
      2. 9.1.2 Power Train Components
        1. 9.1.2.1 Filter Inductor
        2. 9.1.2.2 Output Capacitors
        3. 9.1.2.3 Input Capacitors
        4. 9.1.2.4 Power MOSFETs
      3. 9.1.3 Control Loop Compensation
    2. 9.2 Typical Applications
      1. 9.2.1 Design 1 - High-Efficiency Synchronous Buck Regulator for Telecom Power
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Design 2 - Powering FPGAs Using Flexible 30A Regulator With Small Footprint
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
      3. 9.2.3 Design 3 - Powering Multicore DSPs
      4. 9.2.4 Design 4 - Regulated 12-V Rail with LDO Low-Noise Auxiliary Output for RF Power
      5. 9.2.5 Design 5 - High Power Density Implementation From 3.3-V or 5-V Supply Rail
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Power Stage Layout
      2. 11.1.2 Gate Drive Layout
      3. 11.1.3 Controller Layout
      4. 11.1.4 Thermal Design and Layout
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
      2. 12.1.2 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.