7.3.1 Soft Start

Soft start is engaged when the device is taken out of shutdown mode (EN = logic HIGH) or when voltage is supplied simultaneously to the VIN and EN pins. During soft start, the voltage on V_OUT ramps up in proportion to the rate that the reference voltage is being ramped up. The output voltage is programmed to rise from 0 V to 5 V in 640 µs (typical).

7.3.2 Flash LED Selection

The LM2753 provides a 5-V (typical) fixed voltage to drive a flash LED with a continuous current up to 200 mA (typical). At LED currents above 200 mA (typical), the output of the device is allowed to droop to deliver the desired current to the flash LED. This droop limits the maximum forward voltage and in turn the maximum current that can be supplied to a given LED. Chose LEDs so that the LED forward voltage at the desired maximum LED current does not exceed the output voltage of the LM2753 when loaded down with that same current. TI suggests that the selected LEDs be binned due to the relatively high forward voltage tolerance of flash LEDs. The typical and maximum diode forward voltage depends highly on the manufacturer and their technology. Table 1 lists several suggested manufacturers.

7.3.3 PFM Regulation

The LM2753 achieves its tightly regulated output voltage with pulse-frequency modulated (PFM) regulation. PFM simply means the part only pumps when charge must be delivered to the output in order to keep the output voltage in regulation. When the output voltage is above the target regulation voltage the part idles, consuming minimal supply current with C₁ is connected between V_IN and GND and V_IN is disconnected from V_OUT. In this state, the load current is supplied solely by the charge stored on the output capacitor. As this capacitor discharges and the output voltage falls below the target regulation voltage, the charge pump activates, and charge is delivered to the output. This charge supplies the load current and boosts the voltage on the output capacitor.

The primary benefit of PFM regulation is when output currents are light and the device is predominantly in the low-supply-current idle state. Net supply current is minimal because the part only occasionally needs to recharge the output capacitor by activating the charge pump. With PFM regulation, input and output ripple frequencies vary significantly and are dependent on output current, input voltage, and to a lesser degree, other factors such as temperature, internal switch characteristics, and capacitor characteristics (voltage tolerance, temperature variation).

7.3.4 Output Voltage Ripple

The voltage ripple on the output of the LM2753 is highly dependent on the application conditions. The output capacitance, input voltage, and output current each play a significant part in determining the output voltage ripple. Due to the complexity of the LM2753 operation, providing equations or models to approximate the magnitude of the ripple cannot be easily accomplished. However, the following general statements can be made.

The output capacitor has a significant effect on output voltage ripple magnitude. Ripple magnitude is typically linearly proportional to the output capacitance present. The equivalent series resistance (ESR) of the output capacitor also contributes to the output voltage ripple, as there is effectively an AC-voltage drop across the ESR due to current switching in and out of the capacitor. To keep the voltage ripple small, TI recommends a low-ESR ceramic capacitor on the output. Placing multiple capacitors in parallel can reduce ripple significantly, by both increasing capacitance and reducing ESR. When capacitors are in parallel the ESR of the capacitors are in parallel as well, resulting in a net ESR according to the properties of parallel resistance. Two identical capacitors in parallel have twice the capacitance and half the ESR as compared to a single capacitor if the same type. On a similar note, if a large-value, high-ESR capacitor (tantalum, for example) is to be used as the primary output capacitor, the net ESR can be significantly reduced by placing a low-ESR ceramic capacitor in parallel with this primary output capacitor.

7.3.5 IOUT Pin

An internal FET is connected between the VOUT pin and the IOUT pin of the LM2753 device. When a logic high signal is placed on the FLASH input pin, the internal FET turns on and connects I_OUT to V_OUT in less than 10 ns (typical). If the IOUT pin is not going to be used, the FLASH input pin can be tied to GND, and the IOUT pin can be left unconnected.

In the typical application circuit there is one resistor between VOUT and IOUT and another resistor between IOUT and the flash LED. When a LOW logic signal is placed on the FLASH input pin, the internal FET opens and current flows from V_OUT through both resistors and through the flash LED. When a logic HIGH signal is applied to the Flash input pin the internal FET closes, shorting out the resistor between VOUT and IOUT, and current flows through the second resistor and the Flash LED.

Follow these steps to set the desired current levels for the flash LED:

7.3.6 PWM Brightness Control Procedures

The brightness of a flash LED connected to V_OUT can be linearly varied from zero up to the maximum programmed current level by applying a PWM signal to the EN pin of the LM2753 device. The following procedures describe how to program the LED drive current and adjust the output current level using a PWM signal.

1. To select the maximum desired current level, refer to the IOUT Pin section and follow the steps detailed in Setting Flash Current and Setting Torch Current.
2. Brightness control for torch mode can be implemented by pulsing a signal at the EN pin, while flash is connected to a logic LOW signal. Also, brightness control can also be implemented for flash mode by pulsing a signal on the FLASH pin while the part is already enabled (EN = logic HIGH). LED brightness is proportional to the duty cycle (D) of the PWM signal. For linear brightness control over the full duty cycle adjustment range, the PWM frequency (ƒ) should be limited during torch mode to accommodate the turn-on time (T_ON = 640 µs) of the device. Also, the PWM frequency must be limited during flash mode to accommodate the turnon time (T_FLASH = 10 ns) of the I_OUT output FET.

D × (1/ƒ) > T_ON,FLASH

ƒ_MAX = D_MIN ÷ T_ON,FLASH

If the PWM frequency is much less than 100 Hz, flicker may be seen in the LEDs. For the LM2753, zero duty cycle turns off the LED and a 50% duty cycle results in an average I_OUT being half of the programmed LED current. For example, if the output is programmed for a maximum of 100 mA through the flash LED, a 50% duty cycle results in an average I_LED of 50 mA.

7.3.7 Multi-Level Switch Array

In order to supply high load currents across the entire V_IN operating range, especially at lower V_IN, switches in the charge pump are normally designed to have low ON resistance. However, at high input voltages and low load currents, this low resistance results in high output voltage ripple due to the output capacitor being charged too quickly. To solve this problem, while still being able to deliver the needed output current, the LM2753 has a switch array with multiple switches connected in parallel.

The number of switches used in parallel depends on the input voltage applied to the LM2753. At lower input voltages all paralleled switches are used, and as the input voltage rises, switches are removed from the parallel configuration. The highest switch resistance is achieved as the input voltage reaches the maximum operating voltage, which helps with voltage management.

7.3.8 Thermal Protection

When the junction temperature exceeds 140°C (typical), the LM2753 internal thermal protection circuitry disables the part. This feature protects the device from damage due to excessive power dissipation. The device recovers and operates normally when the junction temperature falls below 125°C (typical). It is important to have good thermal conduction with a proper layout to reduce thermal resistance.

7.3.9 Power Efficiency

Charge-pump efficiency is derived in Equation 1 and Equation 2 (supply current and other losses are neglected for simplicity):

Efficiency is at its highest as G × V_IN approaches V_OUT. Refer to the efficiency graph in Typical Characteristics for the detailed efficiency data.

7.4.1 Enable Mode

The enable logic pin (EN) disables the part and reduces the quiescent current to 0.1 µA (typical). The LM2753 has an active-high EN pin (LOW = shutdown, HIGH = operating). The LM2753 EN pin can be driven with a low-voltage CMOS logic signal (1.5-V logic, 1.8-V logic, etc.). There is an internal 300-kΩ pulldown resistor between the EN and GND pins of the LM2753.

7.4.2 Flash Mode

The flash logic pin (FLASH) controls the internal FET connected between the VOUT and IOUT pins on the LM2753. The LM2753 has an active-HIGH FLASH pin (LOW = shut down, HIGH = operating). A logic HIGH signal must be present on the EN pin before a logic HIGH signal is place on the FLASH input pin. The EN and FLASH input pins can be connected together and controlled with the same logic signal. The turnon time for I_OUT in this configuration will be limited by the turn-on time of the device. The turn-on time for the internal FET is typically 10 ns when the device is already on (EN signal HIGH, V_OUT at 5 V). The LM2753 FLASH pin can be driven with a low-voltage CMOS logic signal (1.5-V logic, 1.8-V logic, etc). There is an internal 300-kΩ pulldown resistor between the FLASH and GND pins of the LM2753.