SNVS422D August   2006  – September 2015 LM2831

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Theory of Operation
      2. 7.3.2 Soft Start
      3. 7.3.3 Output Overvoltage Protection
      4. 7.3.4 Undervoltage Lockout
      5. 7.3.5 Current Limit
      6. 7.3.6 Thermal Shutdown
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 LM2831X Design Example 1
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Inductor Selection
          2. 8.2.1.2.2 Input Capacitor
          3. 8.2.1.2.3 Output Capacitor
          4. 8.2.1.2.4 Catch Diode
          5. 8.2.1.2.5 Output Voltage
        3. 8.2.1.3 Application Curves
      2. 8.2.2 LM2831X Design Example 2
      3. 8.2.3 LM2831X Design Example 3
      4. 8.2.4 LM2831Y Design Example 4
      5. 8.2.5 LM2831Y Design Example 5
      6. 8.2.6 LM2831Z Design Example 6
      7. 8.2.7 LM2831Z Design Example 7
      8. 8.2.8 LM2831X Dual Converters with Delayed Enabled Design Example 8
      9. 8.2.9 LM2831X Buck Converter and Voltage Double Circuit With LDO Follower Design Example 9
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Calculating Efficiency and Junction Temperature
      2. 10.1.2 Thermal Definitions
        1. 10.1.2.1 Silicon Junction Temperature Determination Method 1
      3. 10.1.3 WSON Package
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Layout

10.1 Layout Guidelines

When planning layout there are a few things to consider when trying to achieve a clean, regulated output. The most important consideration is the close coupling of the GND connections of the input capacitor and the catch diode D1. These ground ends should be close to one another and be connected to the GND plane with at least two through-holes. Place these components as close to the IC as possible. Next in importance is the location of the GND connection of the output capacitor, which should be near the GND connections of CIN and D1. There should be a continuous ground plane on the bottom layer of a two-layer board except under the switching node island. The FB pin is a high impedance node and care should be taken to make the FB trace short to avoid noise pickup and inaccurate regulation. The feedback resistors should be placed as close as possible to the IC, with the GND of R1 placed as close as possible to the GND of the IC. The VOUT trace to R2 should be routed away from the inductor and any other traces that are switching. High AC currents flow through the VIN, SW and VOUT traces, so they should be as short and wide as possible. However, making the traces wide increases radiated noise, so the designer must make this trade-off. Radiated noise can be decreased by choosing a shielded inductor. The remaining components should also be placed as close as possible to the IC. See Application Note AN-1229 SNVA054 for further considerations and the LM2831 demo board as an example of a 4-layer layout.

10.1.1 Calculating Efficiency and Junction Temperature

The complete LM2831 DC-DC converter efficiency can be calculated in the following manner.

Equation 15. LM2831 20174820.gif

Or

Equation 16. LM2831 20174822.gif

Calculations for determining the most significant power losses are shown below. Other losses totaling less than 2% are not discussed.

Power loss (PLOSS) is the sum of two basic types of losses in the converter: switching and conduction. Conduction losses usually dominate at higher output loads, whereas switching losses remain relatively fixed and dominate at lower output loads. The first step in determining the losses is to calculate the duty cycle (D):

Equation 17. LM2831 20174810.gif

VSW is the voltage drop across the internal PFET when it is on, and is equal to: 

Equation 18. VSW = IOUT × RDSON

VD is the forward voltage drop across the Schottky catch diode. It can be obtained from the diode manufactures Electrical Characteristics section. If the voltage drop across the inductor (VDCR) is accounted for, the equation becomes:

Equation 19. LM2831 20174821.gif

The conduction losses in the free-wheeling Schottky diode are calculated as follows: 

Equation 20. PDIODE = VD × IOUT × (1-D) 

Often this is the single most significant power loss in the circuit. Care should be taken to choose a Schottky diode that has a low forward voltage drop.

Another significant external power loss is the conduction loss in the output inductor. The equation can be simplified to:

Equation 21. PIND = IOUT2 × RDCR

The LM2831 conduction loss is mainly associated with the internal PFET:

Equation 22. LM2831 20174872.gif

If the inductor ripple current is fairly small, the conduction losses can be simplified to:

Equation 23. PCOND = IOUT2 × RDSON × D

Switching losses are also associated with the internal PFET. They occur during the switch on and off transition periods, where voltages and currents overlap resulting in power loss. The simplest means to determine this loss is to empirically measuring the rise and fall times (10% to 90%) of the switch at the switch node.

Switching power loss is calculated as follows:

Equation 24. PSWR = 1/2(VIN × IOUT × FSW × TRISE)
Equation 25. PSWF = 1/2(VIN × IOUT × FSW × TFALL)
Equation 26. PSW = PSWR + PSWF

Another loss is the power required for operation of the internal circuitry:

Equation 27. PQ = IQ × VIN

IQ is the quiescent operating current, and is typically around 2.5 mA for the 0.55-MHz frequency option.

Typical application power losses are:

Table 10. Power Loss Tabulation

PARAMETER VALUE PARAMETER VALUE
VIN 5 V
VOUT 3.3 V POUT 4.125 W
IOUT 1.25 A
VD 0.45 V PDIODE 188 mW
FSW 550 kHz
IQ 2.5 mA PQ 12.5 mW
TRISE 4 nS PSWR 7 mW
TFALL 4 nS PSWF 7 mW
RDS(ON) 150 mΩ PCOND 156 mW
INDDCR 70 mΩ PIND 110 mW
D 0.667 PLOSS 481 mW
η 88% PINTERNAL 183 mW
Equation 28. ΣPCOND + PSW + PDIODE + PIND + PQ = PLOSS
Equation 29. ΣPCOND + PSWF + PSWR + PQ = PINTERNAL
Equation 30. PINTERNAL = 183 mW

10.1.2 Thermal Definitions

    TJChip junction temperature
    TAAmbient temperature
    RθJC Thermal resistance from chip junction to device case
    RθJAThermal resistance from chip junction to ambient air

Heat in the LM2831 due to internal power dissipation is removed through conduction and/or convection.

    ConductionHeat transfer occurs through cross sectional areas of material. Depending on the material, the transfer of heat can be considered to have poor to good thermal conductivity properties (insulator vs. conductor).

Heat Transfer goes as:

Silicon → package → lead frame → PCB

    Convection: Heat transfer is by means of airflow. This could be from a fan or natural convection. Natural convection occurs when air currents rise from the hot device to cooler air.

Thermal impedance is defined as:

Equation 31. LM2831 20174873.gif

Thermal impedance from the silicon junction to the ambient air is defined as:

Equation 32. LM2831 20174874.gif

The PCB size, weight of copper used to route traces and ground plane, and number of layers within the PCB can greatly effect RθJA. The type and number of thermal vias can also make a large difference in the thermal impedance. Thermal vias are necessary in most applications. They conduct heat from the surface of the PCB to the ground plane. Four to six thermal vias should be placed under the exposed pad to the ground plane if the WSON package is used.

Thermal impedance also depends on the thermal properties of the application operating conditions (Vin, Vo, Io, and so forth), and the surrounding circuitry.

10.1.2.1 Silicon Junction Temperature Determination Method 1

To accurately measure the silicon temperature for a given application, two methods can be used. The first method requires the user to know the thermal impedance of the silicon junction to top case temperature.

Some clarification must be made before we go any further.

RθJC is the thermal impedance from all six sides of an IC package to silicon junction.

RΦJC is the thermal impedance from top case to the silicon junction.

In this data sheet we will use RΦJC so that it allows the user to measure top case temperature with a small thermocouple attached to the top case.

RΦJC is approximately 30°C/Watt for the 6-pin WSON package with the exposed pad. Knowing the internal dissipation from the efficiency calculation given previously, and the case temperature, which can be empirically measured on the bench we have:

Equation 33. LM2831 20174875.gif

Therefore:

Equation 34. Tj = (RΦJC × PLOSS) + TC

From the previous example:

Equation 35. Tj = (RΦJC × PINTERNAL) + TC
Equation 36. Tj = 30°C/W × 0.189 W + TC

The second method can give a very accurate silicon junction temperature.

The first step is to determine RθJA of the application. The LM2831 has overtemperature protection circuitry. When the silicon temperature reaches 165°C, the device stops switching. The protection circuitry has a hysteresis of about 15°C. Once the silicon temperature has decreased to approximately 150°C, the device will start to switch again. Knowing this, the RθJA for any application can be characterized during the early stages of the design one may calculate the RθJA by placing the PCB circuit into a thermal chamber. Raise the ambient temperature in the given working application until the circuit enters thermal shutdown. If the SW-pin is monitored, it will be obvious when the internal PFET stops switching, indicating a junction temperature of 165°C. Knowing the internal power dissipation from the above methods, the junction temperature, and the ambient temperature RθJA can be determined.

Equation 37. LM2831 20174876.gif

Once this is determined, the maximum ambient temperature allowed for a desired junction temperature can be found.

An example of calculating RθJA for an application using the Texas Instruments LM2831 WSON demonstration board is shown below.

The four layer PCB is constructed using FR4 with ½ oz copper traces. The copper ground plane is on the bottom layer. The ground plane is accessed by two vias. The board measures 3 cm × 3 cm. It was placed in an oven with no forced airflow. The ambient temperature was raised to 144°C, and at that temperature, the device went into thermal shutdown.

From the previous example: 

Equation 38. PINTERNAL = 189 mW
Equation 39. LM2831 20174877.gif

If the junction temperature was to be kept below 125°C, then the ambient temperature could not go above 109°C

Equation 40. Tj - (RθJA × PLOSS) = TA
Equation 41. 125°C - (111°C/W × 189 mW) = 104°C

10.1.3 WSON Package

LM2831 20174868.gif Figure 32. Internal WSON Connection

For certain high power applications, the PCB land may be modified to a "dog bone" shape (see Figure 33). By increasing the size of ground plane, and adding thermal vias, the RθJA for the application can be reduced.

10.2 Layout Example

LM2831 20174806.gif Figure 33. 6-Lead WSON PCB Dog Bone Layout