SLOS066AD September 1975 – October 2024 LM124 , LM124A , LM224 , LM224A , LM224K , LM224KA , LM2902 , LM2902B , LM2902BA , LM2902K , LM2902KAV , LM2902KV , LM324 , LM324A , LM324B , LM324BA , LM324K , LM324KA
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |||
---|---|---|---|---|---|---|---|---|
OFFSET VOLTAGE | ||||||||
VOS | Input offset voltage | LM324B | ±0.6 | ±3.0 | mV | |||
TA = –40°C to 85°C | ±4.0 | |||||||
LM324BA | ±0.3 | ±2 | ||||||
TA = –40°C to 85°C | 2.5 | |||||||
dVOS/dT | Input offset voltage drift | RS = 0 Ω | TA = –40°C to 85°C | ±7 | μV/°C | |||
PSRR | Input offset voltage versus power supply | 65 | 100 | dB | ||||
Channel separation | f = 1 kHz to 20 kHz |
120 | dB | |||||
INPUT VOLTAGE RANGE | ||||||||
VCM | Common-mode voltage range | VS = 3 V to 36 V | V– | (V+) – 1.5 | V | |||
VS = 5 V to 36 V | TA = –40°C to 85°C | V– | (V+) – 2 | |||||
CMRR | Common-mode rejection ratio | (V–) ≤ VCM ≤ (V+) – 1.5 V | VS = 3 V to 36 V | 70 | 80 | dB | ||
(V–) ≤ VCM ≤ (V+) – 2 V | VS = 5 V to 36 V | TA = –40°C to 85°C | 65 | 80 | ||||
INPUT BIAS CURRENT | ||||||||
IB | Input bias current | -10 | -35 | nA | ||||
TA = –40°C to 85°C | -60 | |||||||
dIOS/dT | Input offset current drift | TA = –40°C to 85°C | 10 | pA/°C | ||||
IOS | Input offset current | ±0.5 | ±4 | nA | ||||
TA = –40°C to 85°C | ±5 | |||||||
dIOS/dT | Input offset current drift | TA = –40°C to 85°C | 10 | pA/°C | ||||
NOISE | ||||||||
EN | Input voltage noise | f = 0.1 to 10 Hz | 3 | μVPP | ||||
eN | Input voltage noise density | RS = 100 Ω, VI = 0 V, f = 1 kHz (see Figure 7-2 for test circuit) | 35 | nV/√Hz | ||||
INPUT CAPACITANCE | ||||||||
ZID | Differential | 10 || 0.1 | MΩ || pF | |||||
ZICM | Common-mode | 4 || 1.5 | GΩ || pF | |||||
OPEN-LOOP GAIN | ||||||||
AOL | Open-loop voltage gain | VS = 15 V, VO = 1 V to 11 V, RL ≥ 10 kΩ, connected to (V-) | 50 | 100 | V/mV | |||
TA = –40°C to 85°C | 25 | |||||||
FREQUENCY RESPONSE | ||||||||
GBW | Gain-bandwidth product | RL = 1 MΩ, CL = 20 pF (see Figure 7-1 for test circuit) | 1.2 | MHz | ||||
SR | Slew rate | RL = 1 MΩ, CL = 30 pF, VI = ±10 V (see Figure 7-1 for test circuit) | 0.5 | V/μs | ||||
Θm | Phase margin | G = + 1, RL = 10kΩ, CL = 20 pF | 56 | ° | ||||
tS | Settling time | To 0.1%, VS = 5 V, 2-V Step , G = +1, CL = 100 pF | 4 | μs | ||||
Overload recovery time | VIN × gain > VS | 10 | μs | |||||
THD+N | Total harmonic distortion + noise | G = + 1, f = 1 kHz, VO = 3.53 VRMS, VS = 36 V, RL = 100 kΩ, IOUT ≤ 50 µA, BW = 80 kHz | 0.001% | |||||
OUTPUT | ||||||||
VO | Voltage output swing from rail | Positive Rail (V+) | IOUT = -50 µA | 1.35 | 1.5 | V | ||
VO | IOUT = -1 mA | 1.4 | 1.6 | V | ||||
VO | IOUT = -5 mA | 1.5 | 1.75 | V | ||||
VO | Negative Rail (V-) | IOUT = 50 µA | 100 | 150 | mV | |||
VO | IOUT = 1 mA | 0.75 | 1 | V | ||||
VO | VS = 5 V, RL ≤ 10 kΩ connected to (V–) | TA = –40°C to 85°C | 5 | 20 | mV | |||
IO | Output current | VS = 15 V; VO = V-; VID = 1 V | Source | -20(1) | -30 | mA | ||
TA = –40°C to 85°C | -10(1) | mA | ||||||
VS = 15 V; VO = V+; VID = -1 V | Sink | 10(1) | 20 | mA | ||||
TA = –40°C to 85°C | 5(1) | mA | ||||||
VID = -1 V; VO = (V-) + 200 mV | 50 | 85 | μA | |||||
ISC | Short-circuit current | VS = 20 V, (V+) = 10 V, (V-) = -10 V, VO = 0 V | ±40 | ±60 | mA | |||
CLOAD | Capacitive load drive | 100 | pF | |||||
RO | Open-loop output impedance | f = 1 MHz, IO = 0 A | 300 | Ω | ||||
POWER SUPPLY | ||||||||
IQ | Quiescent current per amplifier | VS = 5 V; IO = 0 A | TA = –40°C to 85°C | 240 | 300 | μA | ||
VS = 36 V; IO = 0 A | TA = –40°C to 85°C | 350 | 750 | μA |