SNVS684D November   2010  – March 2016

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics for 3-V LM2936Q
    6. 6.6 Electrical Characteristics for 3.3-V LM2936Q
    7. 6.7 Electrical Characteristics for 5-V LM2936Q
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 High Input Operating Voltage
      2. 7.3.2 Thermal Shutdown (TSD)
      3. 7.3.3 Short-Circuit Current Limit
      4. 7.3.4 Shutdown (SD) Pin
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 External Capacitors
          1. 8.2.2.1.1 Minimum Capacitance
          2. 8.2.2.1.2 ESR Limits
        2. 8.2.2.2 Output Capacitor ESR
        3. 8.2.2.3 Power Dissipation
        4. 8.2.2.4 Estimating Junction Temperature
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Layout

10.1 Layout Guidelines

The dynamic performance of the LM2936Q is dependent on the layout of the PCB. PCB layout practices that are adequate for typical LDOs may degrade the PSRR, noise, or transient performance of the LM2936Q. Best performance is achieved by placing CIN and COUT on the same side of the PCB as the LM2936Q, and as close to the packageas is practical. The ground connections for CIN and COUT must be back to the LM2936Q ground pin using as wide and as short of a copper trace as possible.

Connections using long trace lengths, narrow trace widths, and/or connections through vias must be avoided as these add parasitic inductances and resistances that give inferior performance, especially during transient conditions.

10.2 Layout Examples

LM2936Q soic_bm_snosc48.gif Figure 22. LM2936QHBM SOIC (D) Layout
LM2936Q soic_m_layout.gif Figure 23. LM2936QM SOIC (D) Layout
LM2936Q to252_layout.gif Figure 24. LM2936Q TO-252 (NDP) Layout