SNVS515I September 2007 – January 2018 LM3102
PRODUCTION DATA.
Refer to the PDF data sheet for device specific package drawings
The LM3102 regulation, overvoltage, and current limit comparators are very fast so they will respond to short duration noise pulses. Layout is therefore critical for optimum performance. It must be as neat and compact as possible, and all external components must be as close to their associated pins of the LM3102 as possible.
Refer to Layout Example, the loop formed by CIN, the main and synchronous MOSFET internal to the LM3102, and the PGND pin should be as small as possible. The connection from the PGND pin to CIN should be as short and direct as possible. Vias should be added to connect the ground of CIN to a ground plane, located as close to the capacitor as possible. The bootstrap capacitor CBST should be connected as close to the SW and BST pins as possible, and the connecting traces should be thick. The feedback resistors and capacitor RFB1, RFB2, and CFB should be close to the FB pin.
A long trace running from VOUT to RFB1 is generally acceptable because this is a low-impedance node. Ground RFB2 directly to the AGND pin (pin 7). The output capacitor COUT should be connected close to the load and tied directly to the ground plane. The inductor L should be connected close to the SW pin with as short a trace as possible to reduce the potential for EMI (electromagnetic interference) generation.
If it is expected that the internal dissipation of the LM3102 will produce excessive junction temperature during normal operation, making good use of the PCB ground plane can help considerably to dissipate heat. The exposed pad on the bottom of the LM3102 IC package can be soldered to the ground plane, which should extend out from beneath the LM3102 to help dissipate heat.
The exposed pad is internally connected to the LM3102 IC substrate. Additionally the use of thick traces, where possible, can help conduct heat away from the LM3102. Using numerous vias to connect the die attached pad to the ground plane is a good practice. Judicious positioning of the PCB within the end product, along with the use of any available air flow (forced or natural convection) can help reduce the junction temperature.