SNVS782C October 2010 – August 2015 LM3243
PRODUCTION DATA.
PC board layout is critical to successfully designing a DC-DC converter into a product. A properly planned board layout optimizes the performance of a DC-DC converter and minimizes effects on surrounding circuitry while also addressing manufacturing issues that can have adverse impacts on board quality and final product yield.
Poor board layout can disrupt the performance of a DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce, and resistive voltage loss in the traces. Erroneous signals could be sent to the DC-DC converter device, resulting in poor regulation or instability. Poor layout can also result in re-flow problems leading to poor solder joints between the DSBGA package and board pads. Poor solder joints can result in erratic or degraded performance of the converter.
Minimize resistive losses by using wide traces between the power components and doubling up traces on multiple layers when possible
By its very nature, any switching converter generates electrical noise. The circuit board designer’s challenge is to minimize, contain, or attenuate such switcher-generated noise. A high-frequency switching converter, such as the LM3243, switches Ampere level currents within nanoseconds, and the traces interconnecting the associated components can act as radiating antennas. The following guidelines are offered to help to ensure that EMI is maintained within tolerable levels.
To help minimize radiated noise:
To help minimize conducted noise in the ground-plane:
To help minimize coupling to the DC-DC converter voltage feedback trace:
To help minimize noise coupled back into power supplies:
VBATT Star Connection: It is critically important to use a ‘Star’ connection from VBATT supply to LM3243 PVIN and from VBATT to PA modules as implementing a ‘daisy chain’ supply connection may add noise to the PA output.
The LM3243 package employs a 16-pin (4 × 4) array of 0.24-mm solder balls, with a 0.4-mm pad pitch. A few simple design rules will go a long way to ensuring a good layout.
Use of the DSBGA package requires specialized board layout, precision mounting and careful re-flow techniques, as detailed in TI Application Note AN-1112 DSBGA Wafer Level Chip Scale Package (SNVA009). Please refer to the section Surface Mount Assembly Considerations. For best results in assembly, local alignment fiducials on the PC board should be used to facilitate placement of the device.
The pad style used with DSBGA package must be the NSMD (non-solder mask defined) type. This means that the solder-mask opening is larger than the pad size. This prevents a lip that would otherwise form if the solder-mask and pad overlap, which would hold the device off the surface of the board and interfere with mounting. See SNVA009 for specific instructions how to do this.
The 16-pin package used for LM3243 has 265 micron solder balls and requires 0.225-mm pads for mounting the circuit board. The trace to each pad should enter the pad with a 90°entry angle to prevent debris from being caught in deep corners. Initially, the trace to each pad should be 5.6 mil wide, for a section approximately 5 mil long, as a thermal relief. Then each trace should neck up or down to its optimal width. An important criterion is symmetry to insure the solder bumps on the LM3243 re-flow evenly and that the device solders level to the board. In particular, special attention must be paid to the pads for bumps A1, A3, B1, and B3 since PGND and PVIN are typically connected to large copper planes, inadequate thermal reliefs can result in inadequate re-flow of these bumps.
The DSBGA package is optimized for the smallest possible size in applications with red-opaque or infrared-opaque cases. Because the DSBGA package lacks the plastic encapsulation characteristic of larger devices, it is vulnerable to light. Backside metallization and/or epoxy coating, along with front-side shading by the printed circuit board, reduce this sensitivity. However, the package has exposed die edges that are sensitive to light in the read and infrared range shining on the package’s exposed die edges.