7.3.1 Boost Function

Capacitor C3 and diode D2 in the Functional Block Diagram are used to generate a voltage V_BOOST. The voltage across C3, V_BOOST - V_SW, is the gate drive voltage to the internal NMOS power switch. To properly drive the internal NMOS switch during its on-time, V_BOOST needs to be at least 2.5-V greater than V_SW. A large value of V_BOOST - V_SW is recommended to achieve better efficiency by minimizing both the internal switch ON resistance (R_DS(ON)), and the switch rise and fall times. However, V_BOOST - V_SW should not exceed the maximum operating limit of 5.5 V.

When the LM3405A starts up, internal circuitry from V_IN supplies a 20-mA current to the BOOST pin, flowing out of the BOOST pin into C3. This current charges C3 to a voltage sufficient to turn the switch on. The BOOST pin will continue to source current to C3 until the voltage at the feedback pin is greater than 123 mV.

There are various methods to derive V_BOOST:

1. From the input voltage (V_IN)
2. From the output voltage (V_OUT)
3. From a shunt or series Zener diode
4. From an external distributed voltage rail (V_EXT)

The first method is shown in the Functional Block Diagram. Capacitor C3 is charged via diode D2 by V_IN. During a normal switching cycle, when the internal NMOS power switch is off (T_OFF) (see Figure 11), V_BOOST equals V_IN minus the forward voltage of D2 (V_D2), during which the current in the inductor (L1) forward biases the catch diode D1 (V_D1). Therefore the gate drive voltage stored across C3 is:

When the NMOS switch turns on (T_ON), the switch pin rises to:

Since the voltage across C3 remains unchanged, V_BOOST is forced to rise thus reverse biasing D2. The voltage at V_BOOST is then:

Depending on the quality of the diodes D1 and D2, the gate drive voltage in this method can be slightly less or larger than the input voltage V_IN. For best performance, ensure that the variation of the input supply does not cause the gate drive voltage to fall outside the recommended range:

The second method for deriving the boost voltage is to connect D2 to the output as shown in Figure 12. The gate drive voltage in this configuration is:

Since the gate drive voltage needs to be in the range of 2.5 V to 5.5 V, the output voltage V_OUT should be limited to a certain range. For the calculation of V_OUT, see Output Voltage.

Figure 12. V_BOOST Derived from V_OUT

The third method can be used in the applications where both V_IN and V_OUT are greater than 5.5 V. In these cases, C3 cannot be charged directly from these voltages; instead C3 can be charged from V_IN or V_OUT minus a Zener voltage (V_D3) by placing a Zener diode D3 in series with D2 as shown in Figure 13. When using a series Zener diode from the input, the gate drive voltage is V_IN - V_D3 - V_D2 + V_D1.

Figure 13. V_BOOST Derived from V_IN Through a Series Zener

An alternate method is to place the zener diode D3 in a shunt configuration as shown in Figure 14. A small 350 mW to 500 mW, 5.1-V Zener in a SOT or SOD package can be used for this purpose. A small ceramic capacitor such as a 6.3 V, 0.1-µF capacitor (C5) should be placed in parallel with the Zener diode. When the internal NMOS switch turns on, a pulse of current is drawn to charge the internal NMOS gate capacitance. The 0.1-µF parallel shunt capacitor ensures that the V_BOOST voltage is maintained during this time. Resistor R2 should be chosen to provide enough RMS current to the zener diode and to the BOOST pin. A recommended choice for the zener current (I_ZENER) is 1 mA. The current I_BOOST into the BOOST pin supplies the gate current of the NMOS power switch. It reaches a maximum of around 3.6 mA at the highest gate drive voltage of 5.5 V over the LM3405A operating range.

For the worst case I_BOOST, increase the current by 50%. In that case, the maximum boost current will be:

R2 will then be given by:

For example, let V_IN = 12 V, V_ZENER = 5V, I_ZENER = 1 mA, then:

Figure 14. V_BOOST Derived from V_IN Through a Shunt Zener

The fourth method can be used in an application which has an external low voltage rail, V_EXT. C3 can be charged through D2 from V_EXT, independent of V_IN and V_OUT voltage levels. Again for best performance, ensure that the gate drive voltage, V_EXT - V_D2 + V_D1, falls in the range of 2.5 V to 5.5 V.

7.3.2 Setting the LED Current

LM3405A is a constant current buck regulator. The LEDs are connected between V_OUT and the FB pin as shown in the Typical Application Circuit. The FB pin is at 0.205V in regulation and therefore the LED current I_F is set by V_FB and resistor R1 from FB to ground by the following equation:

I_F should not exceed the 1-A current capability of LM3405A and therefore R1 minimum must be approximately 0.2 Ω. I_F should also be kept above 200 mA for stable operation, and therefore R1 maximum must be approximately 1 Ω. If average LED currents less than 200 mA are desired, the EN/DIM pin can be used for PWM dimming. See LED PWM Dimming.

7.3.3 Output Voltage

The output voltage is primarily determined by the number of LEDs (n) connected from V_OUT to FB pin and therefore V_OUT can be written as:

7.3.4 Enable Mode / Shutdown Mode

The LM3405A has both enable and shutdown modes that are controlled by the EN/DIM pin. Connecting a voltage source greater than 1.8 V to the EN/DIM pin enables the operation of LM3405A, while reducing this voltage below 0.4 V places the part in a low quiescent current (0.3 µA typical) shutdown mode. There is no internal pullup on EN/DIM pin, therefore an external signal is required to initiate switching. Do not allow this pin to float or rise to 0.3 V above V_IN. It should be noted that when the EN/DIM pin voltage rises above 1.8 V while the input voltage is greater than UVLO, there is a finite delay before switching starts. During this delay the LM3405A will go through a power on reset state after which the internal soft-start process commences. The soft-start process limits the inrush current and brings up the LED current (I_F) in a smooth and controlled fashion. The total combined duration of the power on reset delay, soft-start delay and the delay to fully establish the LED current is in the order of 100 µs (see Figure 19).

The simplest way to enable the operation of LM3405A is to connect the EN/DIM pin to V_IN which allows self start-up of LM3405A whenever the input voltage is applied. However, when an input voltage of slow rise time is used to power the application and if both the input voltage and the output voltage are not fully established before the soft-start time elapses, the control circuit will command maximum duty cycle operation of the internal power switch to bring up the output voltage rapidly. When the feedback pin voltage exceeds 0.205 V, the duty cycle will have to reduce from the maximum value accordingly, to maintain regulation. It takes a finite amount of time for this reduction of duty cycle and this will result in a spike in LED current for a short duration as shown in Figure 15. In applications where this LED current overshoot is undesirable, EN/DIM pin voltage can be separately applied and delayed such that V_IN is fully established before the EN/DIM pin voltage reaches the enable threshold. The effect of delaying EN/DIM with respect to V_IN on the LED current is shown in Figure 16. For a fast rising input voltage (200 µs for example), there is no need to delay the EN/DIM signal since soft-start can smoothly bring up the LED current as shown in Figure 17.

Figure 15. Start-Up Response to V_IN With 5-ms Rise Time

Figure 17. Start-Up Response to V_IN With 200-µs Rise Time

Figure 16. Start-Up Response to V_IN With EN/DIM Delayed

7.3.5 LED PWM Dimming

The LED brightness can be controlled by applying a periodic pulse signal to the EN/DIM pin and varying its frequency and/or duty cycle. This so-called PWM dimming method controls the average light output by pulsing the LED current between the set value and zero. A logic high level at the EN/DIM pin turns on the LED current whereas a logic low level turns off the LED current. Figure 18 shows a typical LED current waveform in PWM dimming mode. As explained in the previous section, there is approximately a 100-µs delay from the EN/DIM signal going high to fully establishing the LED current as shown in Figure 19. This 100-µs delay sets a maximum frequency limit for the driving signal that can be applied to the EN/DIM pin for PWM dimming. Figure 20 shows the average LED current versus duty cycle of PWM dimming signal for various frequencies. The applicable frequency range to drive LM3405A for PWM dimming is from 100 Hz to 5 kHz. The dimming ratio reduces drastically when the applied PWM dimming frequency is greater than 5 kHz.

Figure 18. PWM Dimming of LEDs
Using the EN/DIM Pin

Figure 20. Average LED Current vs
Duty Cycle of PWM Dimming Signal at EN/DIM Pin

Figure 19. Start-Up Response to EN/DIM
With I_F = 1 A

7.3.6 Undervoltage Lockout

Undervoltage lockout (UVLO) prevents the LM3405A from operating until the input voltage exceeds 2.74 V (typical). The UVLO threshold has approximately 440 mV of hysteresis, so the part will operate until V_IN drops below 2.3 V (typical). Hysteresis prevents the part from turning off during power up if V_IN is non-monotonic.

7.3.7 Current Limit

The LM3405A uses cycle-by-cycle current limit to protect the internal power switch. During each switching cycle, a current limit comparator detects if the power switch current exceeds 2 A (typical), and turns off the switch until the next switching cycle begins.

7.3.8 Overcurrent Protection

The LM3405A has a built-in overcurrent comparator that compares the FB pin voltage to a threshold voltage that is 60% higher than the internal reference V_REF. Once the FB pin voltage exceeds this threshold level (typically 328 mV), the internal NMOS power switch is turned off, which allows the feedback voltage to decrease towards regulation. This threshold provides an upper limit for the LED current. LED current overshoot is limited to 328 mV/R1 by this comparator during transients.

7.4.1 Thermal Shutdown

Thermal shutdown limits total power dissipation by turning off the internal power switch when the IC junction temperature exceeds 165°C. After thermal shutdown occurs, the power switch does not turn on until the junction temperature drops below approximately 150°C.