SNVSCL9B March 2011 – December 2024 LM3481-Q1
PRODUCTION DATA
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NO. | NAME | ||
1 | ISEN | A | Current sense input pin. Voltage generated across an external sense resistor is fed into this pin. |
2 | UVLO | A | Under voltage lockout pin. A resistor divider from VIN to ground is connected to the UVLO pin. The ratio of these resistances determine the input voltage which allows switching and the hysteresis to disable switching. |
3 | COMP | A | Compensation pin. A resistor and capacitor combination connected to this pin provides compensation for the control loop. |
4 | FB | A | Feedback pin. Inverting input of the error amplifier. |
5 | AGND | G | Analog ground pin. Internal bias circuitry reference. Should be connected to PGND at a single point. |
6 | FA/SYNC/SD | I/A | Frequency adjust, synchronization, and shutdown pin. A resistor connected from this pin to ground sets the oscillator frequency. An external clock signal at this pin will synchronize the controller to the frequency of the clock. A high level on this pin for ≥ 30 µs will turn the device off and the device will then draw 5 µA from the supply typically. |
7 | PGND | G | Power ground pin. External power circuitry reference. Should be connected to AGND at a single point. |
8 | DR | O | Drive pin of the IC. The gate of the external MOSFET should be connected to this pin. |
9 | VCC | O | Driver supply voltage pin. A bypass capacitor must be connected from this pin to PGND. See Section 7.2.1.2.9 section. Do not bias externally. |
10 | VIN | P | Power supply input pin. |