8.2.2.1 Inductor Selection (L)

The inductance can be calculated with Equation 9 and Equation 10 based upon the desired operating frequency.

Equation 9.

Equation 10.

where

• D is the duty cycle
• V_D is the diode forward voltage
• V_DS is the voltage drop across the PFET

The inductor must be rated with Equation 11.

Equation 11.

The inductance value and the resulting ripple is one of the key parameters controlling operating frequency. The second is the inductor ESR that contribute to the steady-state power loss due to current flowing through the inductor.

8.2.2.2 Output Capacitor Selection (C_OUT)

The ESR of the output capacitor times the inductor ripple current is equal to the output ripple of the regulator. However, the V_HYST sets the first-order value of this ripple. As ESR is increased with a given inductance, operating frequency increases as well. If ESR is reduced then the operating frequency reduces.

The use of ceramic capacitors has become a common desire of many power supply designers. However, ceramic capacitors have a very low ESR resulting in a 90° phase shift of the output voltage ripple. This results in low operating frequency and increased output ripple. To fix this problem a low-value resistor must be added in series with the ceramic output capacitor. Although counter intuitive, this combination of a ceramic capacitor and external series resistance provides highly accurate control over the output voltage ripple. Other types capacitor, such as Sanyo POS CAP and OS-CON, Panasonic SP CAP, and Nichicon NA series, are also recommended and may be used without additional series resistance.

For all practical purposes, any type of output capacitor may be used with proper circuit verification.

8.2.2.3 Input Capacitor Selection (C_IN)

A bypass capacitor is required between the input source and ground. It must be located near the source pin of the external PFET. The input capacitor prevents large voltage transients at the input and provides the instantaneous current when the PFET turns on.

The important parameters for the input capacitor are the voltage rating and the RMS current rating. Follow the manufacturer's recommended voltage derating. For high-input voltage applications, low-ESR electrolytic, Nichicon UD series or the Panasonic FK series are available. The RMS current in the input capacitor can be calculated with Equation 12.

Equation 12.

The input capacitor power dissipation can be calculated with Equation 13.

The input capacitor must be able to handle the RMS current and the dissipation. Several input capacitors may be connected in parallel to handle large RMS currents. In some cases it may be much cheaper to use multiple electrolytic capacitors than a single low-ESR, high-performance capacitor such as OS-CON or Tantalum. The capacitance value must be selected such that the ripple voltage created by the switch current pulses is less than 10% of the total DC voltage across the capacitor.

For high VIN conditions (> 28 V), the fast switching, high swing of the internal gate drive introduces unwanted disturbance to the VIN rail and the current limit function can be affected. To eliminate this potential problem, a high-quality ceramic capacitor of 0.1 µF is recommended to filter out the internal disturbance at the VIN pin. This capacitor must be placed right next to the VIN pin for best performance.

8.2.2.4 Programming the Current Limit (R_ADJ)

The current limit is determined with Equation 14 by connecting a resistor (R_ADJ) between input voltage and the ADJ pin, pin 5.

Equation 14.

where

• R_DSON is Drain-Source ON resistance of the external PFET
• I_{CL_ADJ} is 3 µA minimum
• I_{IND_PEAK} = I_LOAD + I_RIPPLE / 2

Using the minimum value for I_{CL_ADJ} (3 µA) ensures that the current limit threshold is set higher than the peak inductor current.

The R_ADJ value must be selected to ensure that the voltage at the ADJ pin does not fall below 3.5 V. With this in mind, R_{ADJ_MAX} = (V_IN – 3.5) / 7 µA. If a larger R_ADJ value is needed to set the desired current limit, either use a PFET with a lower R_DSON or use a current sense resistor as shown in Figure 23.

The current limit function can be disabled by connecting the ADJ pin to ground and ISENSE to VIN.

8.2.2.5 Catch Diode Selection (D1)

The important parameters for the catch diode are the peak current, the peak reverse voltage, and the average power dissipation. The average current through the diode can be calculated with Equation 15.

The off-state voltage across the catch diode is approximately equal to the input voltage. The peak reverse voltage rating must be greater than input voltage. In nearly all cases a Schottky diode is recommended. In low-output voltage applications, a low forward voltage provides improved efficiency. For high-temperature applications, diode leakage current may become significant and require a higher reverse voltage rating to achieve acceptable performance.

8.2.2.6 P-Channel MOSFET Selection (Q1)

The important parameters for the PFET are the maximum Drain-Source voltage (V_DS), the ON resistance (R_DSON), Current rating, and the input capacitance.

The voltage across the PFET when it is turned off is equal to the sum of the input voltage and the diode forward voltage. The V_DS must be selected to provide some margin beyond the input voltage.

PFET drain current, Id, must be rated higher than the peak inductor current, I_IND-PEAK.

Depending on operating conditions, the PGATE voltage may fall as low as V_IN – 8.3 V. Therefore, a PFET must be selected with a V_GS maximum rating greater than the maximum PGATE swing voltage.

As input voltage decreases below 9 V, PGATE swing voltage may also decrease. At 5-V input the PGATE will swing from V_IN to V_IN – 4.6 V. To ensure that the PFET turns on quickly and completely, a low threshold PFET must be used when the input voltage is less than 7 V.

Total power loss in the FET can be approximated using Equation 16.

A value of 10 ns to 20 ns is typical for t_on and t_off.

A PFET must be selected with a turnon rise time of less than 100 ns. Slower rise times will degrade efficiency, can cause false current limiting, and in extreme cases may cause abnormal spiking at the PGATE pin.

The R_DSON is used in determining the current limit resistor value, R_ADJ. Note that the R_DSON has a positive temperature coefficient. At 100°C, the R_DSON may be as much as 150% higher than the 25°C value. This increase in R_DSON must be considered when determining R_ADJ in wide temperature range applications. If the current limit is set based upon 25°C ratings, then false current limiting can occur at high temperature.

Keeping the gate capacitance below 2000 pF is recommended to keep switching losses and transition times low. This will also help keep the PFET drive current low, which will improve efficiency and lower the power dissipation within the controller.

As gate capacitance increases, operating frequency must be reduced and as gate capacitance decreases operating frequency can be increased.

8.2.2.7 Interfacing With the Enable Pin

The enable pin is internally pulled high with clamping at 8 V typical. For normal operation this pin must be left open. To disable the device, the enable pin must be connected to ground externally. If an external voltage source is applied to this pin for enable control, the applied voltage must not exceed the maximum operating voltage level specified in this datasheet, that is 5.5 V. For most applications, an open-drain or open-collector transistor can be used to short this pin to ground to shutdown the device .