Table 3. Buck Converter Design Specifications

8.2.2.1 Custom Design With WEBENCH® Tools

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8.2.2.2 Transformer Turns Ratio

The transformer turns ratio is selected based on the ratio of the primary output voltage to the secondary (isolated) output voltage. In this design example, the two outputs are nearly equal and a 1:1 turns ratio transformer is selected. Therefore, N2 / N1 = 1. If the secondary (isolated) output voltage is significantly higher or lower than the primary output voltage, a turns ratio less than or greater than 1 is recommended. The primary output voltage is normally selected based on the input voltage range such that the duty cycle of the converter does not exceed 50% at the minimum input voltage. This condition is satisfied if VOUT1 < V_{IN_MIN} / 2

8.2.2.3 Total IOUT

The total primary referred load current is calculated by multiplying the isolated output loads by the turns ratio of the transformer as shown in Equation 6.

Equation 6.

8.2.2.4 RFB1, RFB2

The feedback resistors are selected to set the primary output voltage. The selected value for R_FB1 is 1 kΩ. R_FB2 can be calculated using the following equations to set V_OUT1 to the specified value of 10 V. A standard resistor value of 7.32 kΩ is selected for R_FB2.

Equation 7.

Equation 8.

8.2.2.5 Frequency Selection

Equation 1 is used to calculate the value of R_ON required to achieve the desired switching frequency.

Equation 9.

where

For V_OUT1 of 10 V and f_SW of 750 kHz, the calculated value of R_ON is 148 kΩ. A lower value of 130 kΩ is selected for this design to allow for second-order effects at high switching frequency that are not included in Equation 9.

8.2.2.6 Transformer Selection

A coupled inductor or a flyback-type transformer is required for this topology. Energy is transferred from primary to secondary when the low-side synchronous switch of the buck converter is conducting.

The maximum inductor primary ripple current that can be tolerated without exceeding the buck switch peak current limit threshold (0.39-A minimum) is given by Equation 10.

Equation 10.

Using the maximum peak-to-peak inductor ripple current ΔI_L1 from Equation 10, the minimum inductor value is given by Equation 11.

Equation 11.

A higher value of 47 µH is selected to insure the high-side switch current does not exceed the minimum peak current limit threshold.

8.2.2.7 Primary Output Capacitor

In a conventional buck converter the output ripple voltage is calculated as shown in Equation 12.

Equation 12.

To limit the primary output ripple voltage ΔV_OUT1 to approximately 50 mV, an output capacitor C_OUT1 of 0.93 µF is required.

Figure 13 shows the primary winding current waveform (IL1) of a fly-buck converter. The reflected secondary winding current adds to the primary winding current during the buck switch off-time. Because of this increased current, the output voltage ripple is not the same as in conventional buck converter. The output capacitor value calculated in Equation 12 should be used as the starting point. Optimization of output capacitance over the entire line and load range must be done experimentally. If the majority of the load current is drawn from the secondary isolated output, a better approximation of the primary output voltage ripple is given by Equation 13.

Equation 13.

Figure 13. Current Waveforms for C_OUT1 Ripple Calculation

A standard 1-µF, 25-V capacitor is selected for this design. If lower output voltage ripple is required, a higher value should be selected for C_OUT1 and/or C_OUT2.

8.2.2.8 Secondary Output Capacitor

A simplified waveform for secondary output current (I_OUT2) is shown in Figure 14.

Figure 14. Secondary Current Waveforms for C_OUT2 Ripple Calculation

The secondary output current (I_OUT2) is sourced by C_OUT2 during on-time of the buck switch, T_ON. Ignoring the current transition times in the secondary winding, the secondary output capacitor ripple voltage can be calculated using Equation 14.

Equation 14.

For a 1:1 transformer turns ratio, the primary and secondary voltage ripple equations are identical. Therefore, C_OUT2 is chosen to be equal to C_OUT1 (1 µF) to achieve comparable ripple voltages on primary and secondary outputs.

If lower output voltage ripple is required, a higher value should be selected for C_OUT1 and/or C_OUT2.

8.2.2.9 Type III Feedback Ripple Circuit

Type III ripple circuit as described in Ripple Configuration is required for the Fly-Buck topology. Type I and Type II ripple circuits use series resistance and the triangular inductor ripple current to generate ripple at V_OUT and the FB pin. The primary ripple current of a Fly-Buck is the combination or primary and reflected secondary currents as shown in Figure 13. In the fly-buck topology, Type I and Type II ripple circuits suffer from large jitter as the reflected load current affects the feedback ripple.

Figure 15. Type III Ripple Circuit

Selecting the Type III ripple components using the equations from Ripple Configuration ensures that the FB pin ripple is be greater than the capacitive ripple from the primary output capacitor C_OUT1. The feedback ripple component values are chosen as shown in Equation 15.

Equation 15.

The calculated value for Rr is 66 kΩ. This value provides the minimum ripple for stable operation. A smaller resistance should be selected to allow for variations in T_ON, C_OUT1 and other components. For this design, Rr value of 46.4 kΩ is selected.

8.2.2.10 Secondary Diode

The reverse voltage across secondary-rectifier diode D1 when the high-side buck switch is off can be calculated using Equation 16.

Equation 16.

For a V_{IN_MAX} of 95 V and the 1:1 turns ratio of this design, a 100-V Schottky is selected.

8.2.2.11 V_CC and Bootstrap Capacitor

A 1-µF capacitor of 16-V or higher rating is recommended for the V_CC regulator bypass capacitor.

A good value for the BST pin bootstrap capacitor is 0.01-µF with a 16-V or higher rating.

8.2.2.12 Input Capacitor

The input capacitor is typically a combination of a smaller bypass capacitor located near the regulator IC and a larger bulk capacitor. The total input capacitance should be large enough to limit the input voltage ripple to a desired amplitude. For input ripple voltage ΔV_IN, C_IN can be calculated using Equation 17.

Equation 17.

Choosing a ΔV_IN of 0.5 V gives a minimum C_IN of 0.167 μF. A standard value of 0.1 μF is selected for C_BYP in this design. A bulk capacitor of higher value reduces voltage spikes due to parasitic inductance between the power source to the converter. A standard value of 1 μF is selected for C_IN in this design. The voltage ratings of the two input capacitors should be greater than the maximum input voltage under all conditions.

8.2.2.13 UVLO Resistors

UVLO resistors R_UV1 and R_UV2 set the undervoltage lockout threshold and hysteresis according to Equation 18 and Equation 19.

Equation 18.

where

Equation 19.

For a UVLO hysteresis of 2.5 V and UVLO rising threshold of 20 V, Equation 18 and Equation 19 require R_UV1 of 8.25 kΩ and R_UV2 of 127 kΩ and these values are selected for this design example.

8.2.2.14 V_CC Diode

Diode D2 is an optional diode connected between V_OUT1 and the V_CC regulator output pin. When V_OUT1 is more than one diode drop greater than the V_CC voltage, the V_CC bias current is supplied from V_OUT1. This results in reduced power losses in the internal V_CC regulator which improves converter efficiency. V_OUT1 must be set to a voltage at least one diode drop higher than 8.55 V (the maximum V_CC voltage) if D2 is used to supply bias current.