10.1 Layout Guidelines
A proper layout is essential for optimum performance of the circuit. In particular, the following guidelines should be observed:
- CIN: The loop consisting of input capacitor ©IN), VIN pin, and RTN pin carries switching currents. Therefore, place the input capacitor close to the IC, directly across VIN and RTN pins and the connections to these two pins should be direct to minimize the loop area. In general it is not possible to accommodate all of input capacitance near the IC. A good practice is to use a 0.1-µF or 0.47-μF capacitor directly across the VIN and RTN pins close to the IC, and the remaining bulk capacitor as close as possible (see Placement of Bypass Capacitors ).
- CVCC and CBST: The VCC and bootstrap (BST) bypass capacitors supply switching currents to the high- and low-side gate drivers. These two capacitors must also be placed as close to the IC as possible, and the connecting trace lengths and loop area should be minimized (See Figure 26).
- The Feedback trace carries the output voltage information and a small ripple component that is necessary for proper operation of LM34927 device. Therefore take care while routing the feedback trace so avoid coupling any noise to this pin. In particular, feedback trace should not run close to magnetic components, or parallel to any other switching trace.
- SW trace: SW node switches rapidly between VIN and GND every cycle and is therefore a possible source of noise. SW node area should be minimized. In particular SW node should not be inadvertently connected to a copper plane or pour.