7.4.5.1 Fault Operation

If the LM3648 enters a fault condition, the device sets the appropriate flag in the Flags1 and Flags2 Registers (0x0A and 0x0B), and places the device into standby by clearing the Mode Bits ([1],[0]) in the Enable Register. The LM3648 remains in standby until an I²C read of the Flags1 and Flags2 Registers are completed. Upon clearing the flags/faults, the device can be restarted (Flash, Torch, IR, etc.). If the fault is still present, the LM3648 re-enters the fault state and enters standby again.

7.4.5.2 Flash Time-Out

The Flash Time-Out period sets the amount of time that the Flash Current is being sourced from the current source (LED). The LM3648 has 16 timeout levels ranging from 10 ms to 400 ms or 40 ms (see Timing Configuration Register (0x08) for more detail).

7.4.5.3 Overvoltage Protection (OVP)

The output voltage is limited to typically 5 V (see V_OVP spec in the Electrical Characteristics). In situations such as an open LED, the LM3648 raises the output voltage in order to keep the LED current at its target value. When V_OUT reaches 5 V (typical), the overvoltage comparator trips and turns off the internal NFET. When V_OUT falls below the “V_OVP Off Threshold”, the LM3648 begins switching again. The mode bits are cleared, and the OVP flag is set, when an OVP condition is present for three rising OVP edges. This prevents momentary OVP events from forcing the device to shut down.

7.4.5.4 Current Limit

The LM3648 features two selectable inductor current limits that are programmable through the I²C-compatible interface. When the inductor current limit is reached, the LM3648 terminates the charging phase of the switching cycle. Switching resumes at the start of the next switching period. If the overcurrent condition persists, the device operates continuously in current limit.

Because the current limit is sensed in the NMOS switch, there is no mechanism to limit the current when the device operates in Pass Mode (current does not flow through the NMOS in pass mode). In Boost mode or Pass mode if V_OUT falls below 2.3 V, the device stops switching, and the PFET operates as a current source limiting the current to 200 mA. This prevents damage to the LM3648 and excessive current draw from the battery during output short-circuit conditions. The mode bits are not cleared upon a Current Limit event, but a flag is set.

7.4.5.5 NTC Thermistor Input (Torch/Temp)

The TORCH/TEMP pin, when set to TEMP mode, serves as a threshold detector and bias source for negative temperature coefficient (NTC) thermistors. When the voltage at TEMP goes below the programmed threshold, the LM3648 is placed into standby mode. The NTC threshold voltage is adjustable from 200 mV to 900 mV in 100-mV steps. The NTC bias current is set to 50 µA. The NTC detection circuitry can be enabled or disabled via the Enable Register. If enabled, the NTC block turns on and off during the start and stop of a Flash/Torch event.

Additionally, the NTC input looks for an open NTC connection and a shorted NTC connection. If the NTC input falls below 100 mV, the NTC short flag is set, and the device is disabled. If the NTC input rises above 2.3 V, the NTC Open flag is set, and the device is disabled. These fault detections can be individually disabled/enabled via the NTC Open Fault Enable bit and the NTC Short Fault Enable bit.

Figure 26. Temp Detection Diagram

7.4.5.6 Undervoltage Lockout (UVLO)

The LM3648 has an internal comparator that monitors the voltage at IN and forces the LM3648 into standby if the input voltage drops to 2.5 V. If the UVLO monitor threshold is tripped, the UVLO flag bit is set in the Flags1 Register (0x0A). If the input voltage rises above 2.5 V, the LM3648 is not available for operation until there is an I²C read of the Flags1 Register (0x0A). Upon a read, the Flags1 register is cleared, and normal operation can resume if the input voltage is greater than 2.5 V.

7.4.5.7 Thermal Shutdown (TSD)

When the LM3648 die temperature reaches 150°C, the thermal shutdown detection circuit trips, forcing the LM3648 into standby and writing a '1' to the corresponding bit of the Flags1 Register (0x0A) (Thermal Shutdown bit). The LM3648 is only allowed to restart after the Flags1 Register (0x0A) is read, clearing the fault flag. Upon restart, if the die temperature is still above 150°C, the LM3648 resets the Fault flag and re-enters standby.

7.4.5.8 LED and/or VOUT Short Fault

The LED Fault flags read back a '1' if the device is active in Flash or Torch mode and the LED output experiences a short condition. The Output Short Fault flag reads back a '1' if the device is active in Flash or Torch mode and the boost output experiences a short condition. An LED short condition is determined if the voltage at LED goes below 500 mV (typ.) while the device is in Torch or Flash mode. There is a deglitch time of 256 μs before the LED Short flag is valid, and a deglitch time of 2.048 ms before the VOUT Short flag is valid. The LED Short Faults can be reset to '0' by removing power to the LM3648, setting HWEN to '0', setting the SW RESET bit to a '1', or by reading back the Flags1 Register (0x0A on LM3648). The mode bits are cleared upon an LED and/or V_OUT short fault.

7.5.2.1 Data Validity

The data on SDA must be stable during the HIGH period of the clock signal (SCL). In other words, the state of the data line can only be changed when SCL is LOW.

Figure 27. Data Validity Data

A pullup resistor between the controller's VIO line and SDA must be greater than [(VIO-V_OL) / 3mA] to meet the V_OL requirement on SDA. Using a larger pullup resistor results in lower switching current with slower edges, while using a smaller pullup results in higher switching currents with faster edges.

7.5.2.2 Start and Stop Conditions

START and STOP conditions classify the beginning and the end of the I²C session. A START condition is defined as the SDA signal transitioning from HIGH to LOW while SCL line is HIGH. A STOP condition is defined as the SDA transitioning from LOW to HIGH while SCL is HIGH. The I²C master always generates START and STOP conditions. The I²C bus is considered busy after a START condition and free after a STOP condition. During data transmission, the I²C master can generate repeated START conditions. First START and repeated START conditions are equivalent, function-wise.

Figure 28. Start and Stop Conditions

7.5.2.3 Transferring Data

Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) transferred first. Each byte of data has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated by the master. The master releases the SDA line (HIGH) during the acknowledge clock pulse. The LM3648 pulls down the SDA line during the 9th clock pulse, signifying an acknowledge. The LM3648 generates an acknowledge after each byte is received. There is no acknowledge created after data is read from the device.

After the START condition, the I²C master sends a chip address. This address is seven bits long followed by an eighth bit which is a data direction bit (R/W). The LM3648 7-bit address is 0x63. For the eighth bit, a '0' indicates a WRITE and a '1' indicates a READ. The second byte selects the register to which the data is written. The third byte contains data to write to the selected register.

Figure 29. Write Cycle W = Write (SDA = "0") R = Read (SDA = "1") Ack = Acknowledge
(SDA Pulled Down by Either Master or Slave) ID = Chip Address, 63h for LM3648

7.5.2.4 I²C-Compatible Chip Address

The device address for the LM3648 is 1100011 (0x63). After the START condition, the I²C-compatible master sends the 7-bit address followed by an eighth read or write bit (R/W). R/W = 0 indicates a WRITE and R/W = 1 indicates a READ. The second byte following the device address selects the register address to which the data is written. The third byte contains the data for the selected register.

Figure 30. I²C-Compatible Chip Address