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  • LM43603-Q1 3.5-V to 36-V, 3-A Synchronous Step-Down Voltage Converter

    • SNVSA82C April   2015  – October 2017 LM43603-Q1

      PRODUCTION DATA.  

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  • LM43603-Q1 3.5-V to 36-V, 3-A Synchronous Step-Down Voltage Converter
  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed Frequency Peak Current Mode Controlled Step-Down Regulator
      2. 7.3.2  Light Load Operation
      3. 7.3.3  Adjustable Output Voltage
      4. 7.3.4  Enable (EN)
      5. 7.3.5  VCC, UVLO, and BIAS
      6. 7.3.6  Soft-Start and Voltage Tracking (SS/TRK)
      7. 7.3.7  Switching Frequency (RT) and Synchronization (SYNC)
      8. 7.3.8  Minimum ON Time, Minimum OFF Time and Frequency Foldback at Dropout Conditions
      9. 7.3.9  Internal Compensation and CFF
      10. 7.3.10 Bootstrap Voltage (BOOT)
      11. 7.3.11 Power Good (PGOOD)
      12. 7.3.12 Overcurrent and Short-Circuit Protection
      13. 7.3.13 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Stand-by Mode
      3. 7.4.3 Active Mode
      4. 7.4.4 CCM Mode
      5. 7.4.5 Light Load Operation
      6. 7.4.6 Self-Bias Mode
  8. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Custom Design With WEBENCH® Tools
        2. 8.2.2.2  Output Voltage Setpoint
        3. 8.2.2.3  Switching Frequency
        4. 8.2.2.4  Input Capacitors
        5. 8.2.2.5  Inductor Selection
        6. 8.2.2.6  Output Capacitor Selection
        7. 8.2.2.7  Feed-Forward Capacitor
        8. 8.2.2.8  Bootstrap Capacitors
        9. 8.2.2.9  VCC Capacitor
        10. 8.2.2.10 BIAS Capacitors
        11. 8.2.2.11 Soft-Start Capacitors
        12. 8.2.2.12 Undervoltage Lockout Setpoint
        13. 8.2.2.13 PGOOD
      3. 8.2.3 Application Performance Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Compact Layout for EMI Reduction
      2. 10.1.2 Ground Plane and Thermal Considerations
      3. 10.1.3 Feedback Resistors
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Development Support
      1. 11.2.1 Custom Design With WEBENCH® Tools
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
  13. IMPORTANT NOTICE

Package Options

Mechanical Data (Package|Pins)
  • PWP|16
    • MPDS371A
Thermal pad, mechanical data (Package|Pins)
  • PWP|16
    • PPTD297B
Orderable Information
  • snvsa82c_oa
  • snvsa82c_pm
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DATA SHEET

LM43603-Q1 3.5-V to 36-V, 3-A Synchronous Step-Down Voltage Converter

1 Features

  • Qualified for Automotive Applications
  • AEC-Q100 Qualified With the Following Results:
    • Device Temperature Grade 1: –40°C to +125°C Operating Junction Temperature
  • 27-µA Quiescent Current in Regulation
  • High Efficiency at Light Load (DCM and PFM)
  • Meets EN55022/CISPR 22 EMI Standards
  • Integrated Synchronous Rectification
  • Adjustable Frequency Range: 200 kHz to 2.2 MHz (500 kHz default)
  • Frequency Synchronization to External Clock
  • Internal Compensation
  • Stable With Almost any Combination of Ceramic, Polymer, Tantalum, and Aluminum Capacitors
  • Power-Good Flag
  • Soft Start into a Pre-Biased Load
  • Internal Soft Start: 4.1 ms
  • Extendable Soft-Start Time by External Capacitor
  • Output Voltage Tracking Capability
  • Precision Enable to a Program System UVLO
  • Output Short Circuit Protection with Hiccup Mode
  • Overtemperature Thermal Shutdown Protection
  • Create a Custom Design Using the LM43603-Q1 With the WEBENCH® Power Designer

2 Applications

  • Sub-AM Band Automotive
  • Industrial Power Supplies
  • General Purpose Wide VIN Regulation
  • High Efficiency Point-Of-Load Regulation
  • Telecommunications Systems

3 Description

The LM43603-Q1 regulator is an easy-to-use synchronous step-down DC-DC converter capable of driving up to 3 A of load current from an input voltage ranging from 3.5 V to 36 V (42 V absolute maximum). The LM43603-Q1 provides exceptional efficiency, output accuracy, and dropout voltage in a very small solution size. An extended family is available in 0.5-A, 1-A, and 2-A load current options in pin-to-pin compatible packages. Peak current mode control is employed to achieve simple control loop compensation and cycle-by-cycle current limiting. Optional features such as programmable switching frequency, synchronization, power-good flag, precision enable, internal soft-start, extendable soft start, and tracking provide a flexible and easy to use platform for a wide range of applications. Discontinuous conduction and automatic frequency modulation at light loads improve light load efficiency. The family requires few external components and pin arrangement allows simple, optimum PCB layout. Protection features include thermal shutdown, VCC undervoltage lockout, cycle-by-cycle current limit, and output short circuit protection. The LM43603-Q1 device is available in the HTSSOP (PWP) 16-pin leaded package (6.6 mm × 5.1 mm × 1.2 mm). The LM43603A-Q1 version is optimized for PFM operation and recommended for new design. The device is pin-to-pin compatible with LM4360x and LM4600x family.

Device Information

PART NUMBER PACKAGE BODY SIZE
LM43603-Q1 HTSSOP (16) 6.60 mm × 5.10 mm
LM43603A-Q1 HTTSOP (16) 6.60 mm × 5.10 mm


Simplified Schematic

LM43603-Q1 sch_basic01_LM43603Q.png

Radiated Emission Graph
12 VIN to 3.3 VOUT, FS = 500 kHz, IOUT = 3 A

LM43603-Q1 Rad_12VIN3p3V500k3AGr.png

4 Revision History

Changes from B Revision (April 2017) to C Revision

  • Added top navigator icon for TI reference design Go
  • Changed MAX value for VBIAS rising threshold from "3.15" to "3.18" V Go

Changes from A Revision (May 2015) to B Revision

  • Added links for Webench Go
  • Added LM43603A Device InformationGo
  • Added Maximum Operating Junction Temperature Go
  • Added standard FN1 to Thermal Information Go
  • Updating the RPGOOD value on EN = 3.3V and EN = 0V Go
  • Updating Figure 11 to match Figure 87 Go
  • Updating EN Falling Threshold CurveGo
  • Updating EN Rising Threshold Curve Go
  • Updating EN Hysteresis Curve Go
  • Changed Figure 33 into conducted EMI CurveGo
  • Replaced last few sentences of Application Information due to new Webench contentGo
  • Added Equation 25Go
  • Added Equation 26Go
  • Added Figure 73 to Figure 78. Application Performance Curves for VOUT = 5 V, Fs = 500 kHz. Go
  • Changed Figure 86Go
  • Changed Figure 87 Go

Changes from * Revision (April 2015) to A Revision

  • Changed device from Product Preview to Production Data Go
  • Deleted "Super-AM Band"Go
  • Added "BIAS pin voltage should never exceed VIN" to BIAS pin descriptionGo
  • Added "of 10000 hours" to Ab Max FN 2Go
  • Changed info in Vfb rows; in ILKG-FB changed value of from FB=1.011 V to 1.015 VGo
  • Changed VFB = 1.011 V to VFB = 1.015 VGo

5 Pin Configuration and Functions

PWP Package
16-Pin HTSSOP
Top View
LM43603-Q1 po_01_snvsa13.gif

Pin Functions

PIN DESCRIPTION
NAME NO. TYPE(1)
SW 1, 2 P Switching output of the regulator. Internally connected to both power MOSFETs. Connect to power inductor.
CBOOT 3 P Boot-strap capacitor connection for high-side driver. Connect a high quality 470-nF capacitor from CBOOT to SW.
VCC 4 P Internal bias supply output for bypassing. Connect bypass capacitor from this pin to AGND. Do not connect external loading to this pin. Never short this pin to ground during operation.
BIAS 5 P Optional internal LDO supply input. To improve efficiency, TI recommends tying to VOUT when 3.3 V ≤ VOUT ≤ 28 V, or tie to an external 3.3 V or 5 V rail if available. When used, place a bypass capacitor (1 to 10 µF) from this pin to ground. Tie to ground when not in use. Do not float. BIAS pin voltage should never exceed VIN.
SYNC 6 A Clock input to synchronize switching action to an external clock. Use proper high-speed termination to prevent ringing. Connect to ground if not used. Do not float.
RT 7 A Connect a resistor RT from this pin to AGND to program switching frequency. Leave floating for 500 kHz default switching frequency.
PGOOD 8 A Open drain output for power-good flag. Use a 10-kΩ to 100-kΩ pullup resistor to logic rail or other DC voltage no higher than 12 V.
FB 9 A Feedback sense input pin. Connect to the midpoint of feedback divider to set VOUT. Do not short this pin to ground during operation.
AGND 10 G Analog ground pin. Ground reference for internal references and logic. Connect to system ground.
SS/TRK 11 A Soft-start control pin. Leave floating for internal soft-start slew rate. Connect to a capacitor to extend soft start time. Connect to external voltage ramp for tracking.
EN 12 A Enable input to the internal LDO and regulator. High = ON and low = OFF. Connect to VIN, or to VIN through resistor divider,or to an external voltage or logic source. Do not float.
VIN 13,14 P Supply input pins to internal LDO and high side power FET. Connect to power supply and bypass capacitors CIN. Path from VIN pin to high frequency bypass CIN and PGND must be as short as possible.
PGND 15,16 G Power ground pins, connected internally to the low side power FET. Connect to system ground, PAD, AGND, ground pins of CIN and COUT. Path to CIN must be as short as possible.
PAD - - Low impedance connection to AGND. Connect to PGND on PCB. Major heat dissipation path of the die. Must be used for heat sinking to ground plane on PCB.
(1) P = Power, G = Ground, A = Analog

6 Specifications

6.1 Absolute Maximum Ratings

over the recommended operating junction temperature (TJ) range of -40°C to +125°C(1)
PARAMETER MIN MAX UNIT
Input voltages VIN to PGND –0.3 42(2) V
EN to PGND –0.3 VIN + 0.3
FB, RT, SS/TRK to AGND –0.3 3.6
PGOOD to AGND –0.3 15
SYNC to AGND –0.3 5.5
BIAS to AGND –0.3 30 or VIN(3)
AGND to PGND –0.3 0.3
Output voltages SW to PGND –0.3 VIN + 0.3 V
SW to PGND less than 10-ns transients –3.5 42
CBOOT to SW –0.3 5.5
VCC to AGND –0.3 3.6
Storage temperature, Tstg –65 150 °C
Operating junction temperature –40 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) At maximum duty cycle 0.01%
(3) Whichever is lower

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002(1) ±2000 V
Charged-device model (CDM), per AEC Q100-011 ±750
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

over the recommended operating junction temperature (TJ) range of –40°C to +125°C (1)
PARAMETER MIN MAX UNIT
Input voltages VIN to PGND 3.5 36 V
EN –0.3 VIN
FB –0.3 1.1
PGOOD –0.3 12
BIAS input not used –0.3 0.3
BIAS input used 3.3 28 or VIN (2)
AGND to PGND –0.1 0.1
Output voltage VOUT 1 28 V
Output current IOUT 0 3 A
Temperature Operating junction temperature, TJ –40 125 °C
(1) Recommended Operating Conditions indicates conditions for which the device is intended to be functional, but do not ensure specific performance limits. For verified specifications, see Electrical Characteristics.
(2) Whichever is lower.

6.4 Thermal Information

THERMAL METRIC(1)(2)(3) LM43603-Q1 UNIT
PWP (HTSSOP)
16 PINS
RθJA Junction-to-ambient thermal resistance 38.9(4) °C/W
RθJC (Top) Junction-to-case (top) thermal resistance 24.3 °C/W
RθJB Junction-to-board thermal resistance 19.9 °C/W
ψJT Junction-to-top characterization parameter 0.7 °C/W
ψJB Junction-to-board characterization parameter 19.7 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 1.7 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
(2) The package thermal impedance is calculated in accordance with JESD 51-7;
(3) Thermal resistances were simulated on a 4 layer, JEDEC board.
(4) See Figure 98 for RθJA vs Copper Area Curve

6.5 Electrical Characteristics

Limits apply over the recommended operating junction temperature (TJ) range of –40°C to +125°C, unless otherwise stated. Minimum and Maximum limits are specified through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following conditions apply: VIN = 12 V, VOUT = 3.3 V, FS = 500 kHz.
PARAMETER CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE (VIN PIN)
VIN-MIN-ST Minimum input voltage for start-up 3.8 V
ISHDN Shutdown quiescent current VEN = 0 V 1.2 3.1 µA
IQ-NONSW Operating quiescent current (non-switching) from VIN VEN = 3.3 V
VFB = 1.5 V
VBIAS = 3.4 V external		 5 10 µA
IBIAS-NONSW Operating quiescent current (non-switching) from external VBIAS VEN = 3.3 V
VFB = 1.5 V
VBIAS = 3.4 V external		 85 130 µA
IQ-SW Operating quiescent current (switching) VEN = 3.3 V
IOUT = 0 A
RT = open
VBIAS = VOUT = 3.3 V
RFBT = 1 Meg		 27 µA
ENABLE (EN PIN)
VEN-VCC-H Voltage level to enable the internal LDO output VCC VENABLE high level 1.2 V
VEN-VCC-L Voltage level to disable the internal LDO output VCC VENABLE low level 0.525 V
VEN-VOUT-H Precision enable level for switching and regulator output: VOUT VENABLE high level 2 2.20 2.42 V
VEN-VOUT-HYS Hysteresis voltage between VOUT precision enable and disable thresholds VENABLE hysteresis –290 mV
ILKG-EN Enable input leakage current VEN = 3.3 V 0.85 1.75 µA
INTERNAL LDO (VCC and BIAS PINS)
VCC Internal LDO output voltage VCC VIN ≥ 3.8 V 3.28 V
VCC-UVLO Undervoltage lockout (UVLO) thresholds for VCC VCC rising threshold 3.1 V
Hysteresis voltage between rising and falling thresholds –520 mV
VBIAS-ON Internal LDO input change over threshold to BIAS VBIAS rising threshold 2.94 3.18 V
Hysteresis voltage between rising and falling thresholds -75 mV
VOLTAGE REFERENCE (FB PIN)
VFB Feedback voltage TJ = 25 ºC 1.012 1.015 1.019 V
TJ = -40 ºC to 125 ºC 0.999 1.015 1.032
ILKG-FB Input leakage current at FB pin FB = 1.015 V 0.2 65 nA
THERMAL SHUTDOWN
TSD (1) Thermal shutdown Shutdown threshold 160 ºC
Recovery threshold 150 ºC
CURRENT LIMIT AND HICCUP
IHS-LIMIT Peak inductor current limit 4.4 5.5 6.4 A
ILS-LIMIT Inductor current valley limit 2.6 3 3.3 A
SOFT START (SS/TRK PIN)
ISSC Soft-start charge current 1.25 2 2.75 µA
RSSD Soft-start discharge resistance UVLO, TSD, OCP, or EN = 0 V 18 kΩ
POWER GOOD (PGOOD PIN)
VPGOOD-HIGH Power-good flag over voltage tripping threshold % of FB voltage 110% 113%
VPGOOD-LOW Power-good flag under voltage tripping threshold % of FB voltage 77% 88%
VPGOOD-HYS Power-good flag recovery hysteresis % of FB voltage 6%
RPGOOD PGOOD pin pulldown resistance when power bad VEN = 3.3 V 69 150 Ω
VEN = 0 V 150 350
MOSFETS (2)
RDS-ON-HS High-side MOSFET ON-resistance IOUT = 1 A
VBIAS = VOUT = 3.3 V		 120 mΩ
RDS-ON-LS Low-side MOSFET ON-resistance IOUT = 1 A
VBIAS = VOUT = 3.3 V		 65 mΩ
(1) Ensured by design
(2) Measured at pins

6.6 Timing Requirements

MIN NOM MAX UNIT
CURRENT LIMIT AND HICCUP
NOC Hiccup wait cycles when LS current limit tripped 32 Cycles
TOC Hiccup retry delay time 5.5 ms
SOFT START (SS/TRK PIN)
TSS Internal soft-start time when SS pin open circuit 4.1 ms
POWER GOOD (PGOOD PIN)
TPGOOD-RISE Power-good flag rising transition deglitch delay 220 µs
TPGOOD-FALL Power-good flag falling transition deglitch delay 220 µs

6.7 Switching Characteristics

Limits apply over the recommended operating junction temperature (TJ) range of –40°C to +125°C, unless otherwise stated. Minimum and Maximum limits are specified through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following conditions apply: VIN = 12 V, VOUT = 3.3 V, FS = 500 kHz.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SW (SW PIN)
tON-MIN(1) Minimum high side MOSFET ON time 125 165 ns
tOFF-MIN(1) Minimum high side MOSFET OFF time 200 250 ns
OSCILLATOR (SW and SYNC PINS)
FOSC-DEFAULT Oscillator default frequency RT pin open circuit 425 500 580 kHz
FADJ Minimum adjustable frequency With 1% resistors at RT pin 200 kHz
Maximum adjustable frequency 2200 kHz
Frequency adjust accuracy 10%
VSYNC-HIGH Sync clock high level threshold 2 V
VSYNC-LOW Sync clock low level threshold 0.4 V
DSYNC-MAX Sync clock maximum duty cycle 90%
DSYNC-MIN Sync clock minimum duty cycle 10%
TSYNC-MIN Mininum sync clock ON and OFF time 80 ns
(1) Ensured by design

6.8 Typical Characteristics

Unless otherwise specified, VIN = 12 V, VOUT = 3.3 V, FS = 500 kHz, L = 6.8 µH and room temperature. See Application Performance Curves for bill of materials for other VOUT and FS combinations.
LM43603-Q1 3p3V_500k_Eff_Gr.png
VOUT = 3.3 V FS = 500 kHz
Figure 1. Efficiency
LM43603-Q1 5V_500k_Eff_Gr.png
VOUT = 5 V FS = 500 kHz
Figure 3. Efficiency
LM43603-Q1 5V_2M_Eff_Gr.png
VOUT = 5 V FS = 2.2 MHz
Figure 5. Efficiency
LM43603-Q1 3p3_500k_Reg_Gr.png
VOUT = 3.3V FS = 500 kHz
Figure 7. VOUT Regulation
LM43603-Q1 5V_500k_Reg_Gr.png
VOUT = 5 V FS = 500 kHz
Figure 9. VOUT Regulation
LM43603-Q1 5V_2M_Reg_Gr_Update.png
VOUT = 5 V FS = 2.2 MHz
Figure 11. VOUT Regulation
LM43603-Q1 3p3V_500k_Drop_Gr.png
VOUT = 3.3 V FS = 500 kHz
Figure 13. Dropout Curve
LM43603-Q1 5V_500k_Drop_Gr.png
VOUT = 5 V FS = 500 kHz
Figure 15. Dropout Curve
LM43603-Q1 5V_2M_Drop_Gr.png
VOUT = 5 V FS = 2.2 MHz
Figure 17. Dropout Curve
LM43603-Q1 EN_DOWN.png Figure 19. EN Falling Threshold
LM43603-Q1 EN_Hyst.png Figure 21. EN Hysteresis
LM43603-Q1 HSRDSON.png Figure 23. High-Side FET On Resistance vs Junction Temperature
LM43603-Q1 HSILIM.png Figure 25. High-Side Current Limit vs Junction Temperature
LM43603-Q1 PGOVPUP.png Figure 27. PGOOD OVP Falling Threshold vs Junction Temperature
LM43603-Q1 PGUVPDWN.png Figure 29. PGOOD UVP Falling Threshold vs Junction Temperature
LM43603-Q1 Rad_12VIN3p3V500k3AGr.png
VOUT = 3.3 V FS = 500 kHz IOUT = 3 A
Figure 31. Radiated EMI Curve
LM43603-Q1 Con_12VIN3p3V500k3AGr.png
VOUT = 3.3 V FS = 500 kHz IOUT = 3 A
Cd = 47 µF Lin = 1 µH CIN4 = 68 µF
Figure 33. Conducted EMI Curve
LM43603-Q1 5V_200k_Eff_Gr.png
VOUT = 5V FS = 200 kHz
Figure 2. Efficiency
LM43603-Q1 5V_1M_Eff_Gr.png
VOUT = 5 V FS = 1 MHz
Figure 4. Efficiency
LM43603-Q1 12V_500k_Eff_Gr.png
VOUT = 12 V FS = 500 kHz
Figure 6. Efficiency
LM43603-Q1 5V_200k_Reg_Gr.png
VOUT = 5 V FS = 200 kHz
Figure 8. VOUT Regulation
LM43603-Q1 5V_1M_Reg_Gr.png
VOUT = 5 V FS = 1 MHz
Figure 10. VOUT Regulation
LM43603-Q1 12V_500k_Reg_Gr.png
VOUT = 12 V FS = 500 kHz
Figure 12. VOUT Regulation
LM43603-Q1 5V_200k_Drop_Gr.png
VOUT = 5 V FS = 200 kHz
Figure 14. Dropout Curve
LM43603-Q1 5V_1M_Drop_Gr.png
VOUT = 5 V FS = 1 MHz
Figure 16. Dropout Curve
LM43603-Q1 12V_500k_Drop_Gr.png
VOUT = 12 V FS = 500 kHz
Figure 18. Dropout Curve
LM43603-Q1 EN_UP.png Figure 20. EN Rising Threshold
LM43603-Q1 VFB.png Figure 22. FB Voltage vs Junction Temperature
LM43603-Q1 LSRDSON.png Figure 24. Low-Side FET On Resistance vs Junction Temperature
LM43603-Q1 LSILIM.png Figure 26. Low-Side Current Limit vs Junction Temperature
LM43603-Q1 PGOVPDOWN.png Figure 28. PGOOD OVP Rising Threshold vs Junction Temperature
LM43603-Q1 PGUVPUP.png Figure 30. PGOOD UVP Rising Threshold vs Junction Temperature
LM43603-Q1 Rad_12VIN5V500k3AGr.png
VOUT = 5 V FS = 500 kHz IOUT = 3 A
Figure 32. Radiated EMI Curve
LM43603-Q1 Con_12VIN5V500k3AGr.png
VOUT = 5 V FS = 500 kHz IOUT = 3 A
Cd = 47 µF Lin = 1 µH CIN4 = 68 µF
Figure 34. Conducted EMI Curve

 
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