SNAS276G May   2005  – September 2015 LM4550B

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Comditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  ADC inputs and Outputs
      2. 8.3.2  Analog Mixing: MIX1
      3. 8.3.3  DAC Mixing and 3D Processing
      4. 8.3.4  Analog Mixing: MIX2
      5. 8.3.5  Stereo Mix
      6. 8.3.6  Stereo Outputs
      7. 8.3.7  Mono Output
      8. 8.3.8  Analog Loopthrough And Digital Loopback
      9. 8.3.9  Resets
      10. 8.3.10 Multiple Codecs
        1. 8.3.10.1 Extended AC Link
        2. 8.3.10.2 Secondary Codec Register Access
          1. 8.3.10.2.1 SLOT 0: TAG bits in Output Frames (Controller to Codec)
          2. 8.3.10.2.2 Extended Audio ID Register (28h): Support for Multiple Codecs
          3. 8.3.10.2.3 CODEC Chaining
    4. 8.4 Device Functional Modes
      1. 8.4.1 Test Modes
    5. 8.5 Programming
      1. 8.5.1 AC Link Serial Interface Protocol
        1. 8.5.1.1 AC Link Output Frame: SDATA_OUT, Controller Output to LM4550B Input
          1. 8.5.1.1.1 SDATA_OUT: Slot 0 - Tag Phase
          2. 8.5.1.1.2 SDATA_OUT: Slot 1 - Read/Write, Control Address
          3. 8.5.1.1.3 SDATA_OUT: Slot 2 - Control Data
          4. 8.5.1.1.4 SDATA_OUT: Slots 3 & 4 - PCM Playback Left/Right Channels
          5. 8.5.1.1.5 SDATA_OUT: Slots 7 & 8 - PCM Playback Left/Right Surround
          6. 8.5.1.1.6 SDATA_OUT: Slots 6 & 9 - PCM Playback (Center/LFE)
          7. 8.5.1.1.7 SDATA_OUT: Slots 5, 10, 11, 12 - Reserved
        2. 8.5.1.2 AC Link Input Frame: SDATA_IN, Controller Input from LM4550B Output
          1. 8.5.1.2.1 SDATA_IN: Slot 0 - Codec/Slot Status Bits
          2. 8.5.1.2.2 SDATA_IN: Slot 1 - Status Address / Slot Request Bits
          3. 8.5.1.2.3 SDATA_IN: Slot 2 - Status Data
          4. 8.5.1.2.4 SDATA_IN: Slot 3 - PCM Record Left Channel
          5. 8.5.1.2.5 SDATA_IN: Slot 4 - PCM Record Right Channel
          6. 8.5.1.2.6 SDATA_IN: Slots 5 to 12 - Reserved
    6. 8.6 Register Maps
      1. 8.6.1  LM4550B Register Map
      2. 8.6.2  Register Descriptions
      3. 8.6.3  Reset Register (00h)
      4. 8.6.4  Master Volume Register (02h)
      5. 8.6.5  Headphone Volume Register (04h)
      6. 8.6.6  Mono Volume Register (06h)
      7. 8.6.7  PC Beep Volume Register (0Ah)
      8. 8.6.8  Mixer Input Volume Registers (Index 0Ch - 18h)
      9. 8.6.9  Record Select Register (1Ah)
      10. 8.6.10 Record Gain Register (1Ch)
      11. 8.6.11 General Purpose Register (20h)
      12. 8.6.12 3D Control Register (22h)
      13. 8.6.13 Power-Down Control / Status Register (26h)
      14. 8.6.14 Extended Audio Id Register (28h)
      15. 8.6.15 Extended Audio Status/control Register (2Ah)
      16. 8.6.16 Sample Rate Control Registers (2Ch, 32h)
      17. 8.6.17 Chain-in Control Register (74h)
      18. 8.6.18 Vendor ID Registers (7Ch, 7Eh)
      19. 8.6.19 Reserved Registers
      20. 8.6.20 Low Power Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Improving System Performance
      2. 9.1.2 Backwards Compatibility
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
    3. 9.3 System Examples
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
  12. 12Device and Documentation Support
    1. 12.1 Community Resources
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Description (continued)

Each mixer input has separate gain, attenuation and mute control and the mixers drive 1 mono and 2 stereo outputs, each with attenuation and mute control. The LM4550B provides a stereo headphone amplifier as one of its stereo outputs and also supports TI's 3D sound stereo enhancement and a comprehensive sample rate conversion capability. The sample rate for the ADCs and DACs can be programmed separately with a resolution of 1 Hz to convert any rate from 4 kHz to 48 kHz. Sample timing from the ADCs and sample request timing for the DACs are completely deterministic to ease task scheduling and application software development. These features together with an extended temperature range also make the LM4550B suitable for non-PC codec applications.

The LM4550B features the ability to connect several codecs together in a system to provide up to 6 simultaneous channels of streaming data on output frames (controller to codec) for surround sound applications. Such systems can also support up to 8 simultaneous channels of streaming data on input frames (codec to controller). Multiple codec systems can be built either using the standard AC Link configuration (that is, of one serial data signal to the controller per codec) or using a unique TI feature for chaining codecs together. This chain feature shares only a single data signal to the controller among multiple codecs.

The AC '97 architecture separates the analog and digital functions of the PC audio system allowing both for system design flexibility and increased performance.