SNVSA46B June   2014  – January 2018 LM46001

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
      2.      Radiated Emission Graph VOUT = 3.3 V, VIN = 24 V, FS= 500 kHz, IOUT = 1 A
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed-Frequency, Peak-Current Mode Controlled Step-Down Regulator
      2. 7.3.2  Light Load Operation
      3. 7.3.3  Adjustable Output Voltage
      4. 7.3.4  Enable (ENABLE)
      5. 7.3.5  VCC, UVLO, and BIAS
      6. 7.3.6  Soft-Start and Voltage Tracking (SS/TRK)
      7. 7.3.7  Switching Frequency (RT) and Synchronization (SYNC)
      8. 7.3.8  Minimum ON-Time, Minimum OFF-Time and Frequency Foldback at Dropout Conditions
      9. 7.3.9  Internal Compensation and CFF
      10. 7.3.10 Bootstrap Voltage (CBOOT)
      11. 7.3.11 Power Good (PGOOD)
      12. 7.3.12 Overcurrent and Short-Circuit Protection
      13. 7.3.13 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Stand-by Mode
      3. 7.4.3 Active Mode
      4. 7.4.4 CCM Mode
      5. 7.4.5 Light Load Operation
      6. 7.4.6 Self-Bias Mode
  8. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Custom Design With WEBENCH® Tools
        2. 8.2.2.2  Output Voltage Setpoint
        3. 8.2.2.3  Switching Frequency
        4. 8.2.2.4  Input Capacitors
        5. 8.2.2.5  Inductor Selection
        6. 8.2.2.6  Output Capacitor Selection
        7. 8.2.2.7  Feed-Forward Capacitor
        8. 8.2.2.8  Bootstrap Capacitors
        9. 8.2.2.9  VCC Capacitor
        10. 8.2.2.10 BIAS Capacitors
        11. 8.2.2.11 Soft-Start Capacitors
        12. 8.2.2.12 Undervoltage Lockout Setpoint
        13. 8.2.2.13 PGOOD
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Compact Layout for EMI Reduction
      2. 10.1.2 Ground Plane and Thermal Considerations
      3. 10.1.3 Feedback Resistors
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Custom Design With WEBENCH® Tools
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

Limits apply over the recommended operating junction temperature (TJ) range of –40°C to +125°C, unless otherwise stated. Minimum and maximum limits are specified through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following conditions apply: VIN = 24 V, VOUT = 3.3 V, FS = 500 kHz.
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
SUPPLY VOLTAGE (VIN PINS)
VIN-MIN-ST Minimum input voltage for startup 3.8 V
ISHDN Shutdown quiescent current VEN = 0 V 2.3 5 µA
IQ-NONSW Operating quiescent current (non-switching) from VIN VEN = 3.3 V
VFB = 1.5 V
VBIAS = 3.4 V external		 7 13 µA
IBIAS-NONSW Operating quiescent current (non-switching) from external VBIAS VEN = 3.3 V
VFB = 1.5 V
VBIAS = 3.4 V external		 85 140 µA
IQ-SW Operating quiescent current (switching) VEN = 3.3 V
IOUT = 0 A
RT = open
VBIAS = VOUT = 3.3 V
RFBT = 1 Meg		 24 µA
ENABLE (EN PIN)
VEN-VCC-H Voltage level to enable the internal LDO VENABLE high level 1.2 V
VEN-VCC-L Voltage level to disable the internal LDO VENABLE low level 0.4 V
VEN-VOUT-H Precision enable level for switching and regulator output VENABLE high level 2 2.1 2.42 V
VEN-VOUT-HYS Hysteresis voltage between VOUT precision enable and disable thresholds VENABLE hysteresis –305 mV
ILKG-EN Enable input leakage current VEN = 3.3 V 0.8 1.75 µA
INTERNAL LDO (VCC PIN AND BIAS PIN)
VCC Internal LDO output voltage VCC VIN ≥ 3.8 V 3.3 V
VCC-UVLO Undervoltage lockout (UVLO) thresholds for VCC VCC rising threshold 3.14 V
Hysteresis voltage between rising and falling thresholds –567 mV
VBIAS-ON Internal LDO input change over threshold to BIAS VBIAS rising threshold 2.96 3.2 V
Hysteresis voltage between rising and falling thresholds –71 mV
VOLTAGE REFERENCE (FB PIN)
VFB Feedback voltage TJ = 25°C 1.009 1.016 1.023 V
TJ = –40°C to 85°C 0.999 1.016 1.031
TJ = –40°C to 125°C 0.999 1.016 1.039
ILKG-FB Input leakage current at FB pin FB = 1.016 V 0.2 65 nA
THERMAL SHUTDOWN
TSD(1) Thermal shutdown Shutdown threshold 160 °C
Recovery threshold 150 °C
CURRENT LIMIT AND HICCUP
IHS-LIMIT Peak inductor current limit 2.07 2.45 2.71 A
ILS-LIMIT Valley inductor current limit 0.94 1.1 1.25 A
SOFT START (SS/TRK PIN)
ISSC Soft-start charge current 1.17 2.2 2.85 µA
RSSD Soft-start discharge resistance UVLO, TSD, OCP, or EN = 0 V 16 kΩ
POWER GOOD (PGOOD PIN)
VPGOOD-HIGH Power-good flag overvoltage tripping threshold % of FB voltage 110% 113%
VPGOOD-LOW Power-good flag undervoltage tripping threshold % of FB voltage 83% 90%
VPGOOD-HYS Power-good flag recovery hysteresis % of FB voltage 6%
RPGOOD PGOOD pin pulldown resistance when power bad VEN = 3.3 V 40 125 Ω
VEN = 0 V 60 150
MOSFETS(2)
RDS-ON-HS High-side MOSFET ON-resistance IOUT = 1 A
VBIAS = VOUT = 3.3 V		 419 mΩ
RDS-ON-LS Low-side MOSFET ON-resistance IOUT = 1 A
VBIAS = VOUT = 3.3 V		 231 mΩ
(1) Specified by design. Not production tested
(2) Measured at package pins.