7.3.1 Fixed Frequency Peak Current Mode Controlled Step-Down Regulator

The following operating description of the LM46002-Q1 refer to the Functional Block Diagram and to the waveforms in Figure 33. The LM46002-Q1 is a step-down buck regulator with both high-side (HS) switch and low-side (LS) switch (synchronous rectifier) integrated. The LM46002-Q1 supplies a regulated output voltage by turning on the HS and LS NMOS switches with controlled ON-time. During the HS switch ON-time, the SW pin voltage V_SW swings up to approximately V_IN, and the inductor current I_L increases with a linear slope (V_IN – V_OUT) / L. When the HS switch is turned off by the control logic, the LS switch is turned on after a anti-shoot-through dead time. Inductor current discharges through the LS switch with a slope of –V_OUT / L. The control parameter of buck converters are defined as duty cycle D = t_ON / T_SW, where t_ON is the HS switch ON-time and T_SW is the switching period. The regulator control loop maintains a constant output voltage by adjusting the duty cycle D. In an ideal buck converter, where losses are ignored, D is proportional to the output voltage and inversely proportional to the input voltage: D = V_OUT / V_IN.

Figure 33. SW Node and Inductor Current Waveforms in Continuous Conduction Mode (CCM)

The LM46002-Q1 synchronous buck converter employs peak current mode control topology. A voltage feedback loop is used to get accurate DC voltage regulation by adjusting the peak current command based on voltage offset. The peak inductor current is sensed from the HS switch and compared to the peak current to control the ON-time of the HS switch. The voltage feedback loop is internally compensated, which allows for fewer external components, makes it easy to design, and provides stable operation with almost any combination of output capacitors. The regulator operates with fixed switching frequency in CCM and DCM . At very light load, the LM46002-Q1 operates in PFM to maintain high efficiency, and the switching frequency decreases with reduced load current.

7.3.2 Light Load Operation

DCM operation is employed in the LM46002-Q1 when the inductor current valley reaches zero. The LM46002-Q1 is in DCM when load current is less than half of the peak-to-peak inductor current ripple in CCM. In DCM, the LS switch is turned off when the inductor current reaches zero. Switching loss is reduced by turning off the LS FET at zero current, and the conduction loss is lowered by not allowing negative current conduction. Power conversion efficiency is higher in DCM than CCM under the same conditions.

In DCM, the HS switch ON-time reduces with lower load current. When either the minimum HS switch ON-time (t_ON-MIN) or the minimum peak inductor current (I_PEAK-MIN) is reached, the switching frequency decreases to maintain regulation. At this point, the LM46002-Q1 operates in PFM. In PFM, switching frequency is decreased by the control loop when load current reduces to maintain output voltage regulation. Switching loss is further reduced in PFM operation due to less frequent switching actions. Figure 34 shows an example of switching frequency decreases with decreased load current.

Figure 34. Switching Frequency Decreases with Lower Load Current in PFM Operation
V_OUT = 5 V F_S = 1 MHz

In PFM operation, a small positive DC offset is required at the output voltage to activate the PFM detector. The lower the frequency in PFM, the more DC offset is needed at V_OUT. See the Typical Characteristics for typical DC offset at very light load. If the DC offset on V_OUT is not acceptable for a given application, TI recommends a static load at output to reduce or eliminate the offset. Lowering values of the feedback divider R_FBT and R_FBB can also serve as a static load. In conditions with low V_IN and/or high frequency, the LM46002-Q1 may not enter PFM mode if the output voltage cannot be charged up to provide the trigger to activate the PFM detector. Once the LM46002-Q1 is operating in PFM mode at higher V_IN, it remains in PFM operation when V_IN is reduced.

7.3.3 Adjustable Output Voltage

The voltage regulation loop in the LM46002-Q1 regulates output voltage by maintaining the voltage on FB pin (V_FB) to be the same as the internal REF voltage (V_REF). A resistor divider pair is needed to program the ratio from output voltage V_OUT to V_FB. The resistor divider is connected from the V_OUT of the LM46002-Q1 to ground with the mid-point connecting to the FB pin.

Figure 35. Output Voltage Setting

The voltage reference system produces a precise voltage reference overtemperature. The internal REF voltage is 1.011 V, typically. To program the output voltage of the LM46002-Q1 to be a certain value V_OUT, R_FBB can be calculated with a selected R_FBT by

Equation 1.

The choice of the R_FBT depends on the application. R_FBT in the range from 10 kΩ to 100 kΩ is recommended for most applications. A lower R_FBT value can be used if static loading is desired to reduce V_OUT offset in PFM operation. Lower R_FBT will reduce efficiency at very light load. Less static current goes through a larger R_FBT and might be more desirable when light load efficiency is critical. But R_FBT larger than 1 MΩ is not recommended because it makes the feedback path more susceptible to noise. Larger R_FBT value requires more carefully designed feedback path on the PCB. The tolerance and temperature variation of the resistor dividers affect the output voltage regulation. It is recommended to use divider resistors with 1% tolerance or better and temperature coefficient of 100 ppm or lower.

If the resistor divider is not connected properly, output voltage cannot be regulated since the feedback loop is broken. If the FB pin is shorted to ground, the output voltage is driven close to V_IN, since the regulator detects very low voltage on the FB pin and tries to regulate it up. The load connected to the output could be damaged under such a condition. Do not short FB pin to ground when the LM46002-Q1 is enabled. It is important to route the feedback trace away from the noisy area of the PCB. For more layout recommendations, refer to the Layout section.

7.3.4 Enable (ENABLE)

Voltage on the ENABLE pin (V_EN) controls the ON or OFF functionality of the LM46002-Q1. Applying a voltage less than 0.4 V to the ENABLE input shuts down the operation of the LM46002-Q1. In shutdown mode the quiescent current drops to typically 2.3 µA at V_IN = 24 V.

The internal LDO output voltage V_CC is turned on when V_EN is higher than 1.2 V. The switching action and output regulation are enabled when V_EN is greater than 2.1 V (typical). The LM46002-Q1 supplies regulated output voltage when enabled and output current up to 2 A.

The ENABLE pin is an input and cannot be open circuit or floating. The simplest way to enable the operation of the LM46002-Q1 is to connect the ENABLE pin to VIN pins directly. This allows self-start-up when V_IN is within the operation range.

Many applications will benefit from the employment of an enable divider R_ENT and R_ENB in Figure 36 to establish a precision system UVLO level for the stage. System UVLO can be used for supplies operating from utility power as well as battery power. It can be used for sequencing, ensuring reliable operation, or supply protection, such as a battery. An external logic signal can also be used to drive EN input for system sequencing and protection.

Figure 36. System UVLO By Enable Dividers

7.3.5 VCC, UVLO and BIAS

The LM46002-Q1 integrates an internal LDO to generate V_CC for control circuitry and MOSFET drivers. The nominal voltage for V_CC is 3.2 V. The VCC pin is the output of the LDO and must be properly bypassed. Place a high-quality ceramic capacitor with 2.2-µF to 10-µF capacitance and 6.3-V or higher rated voltage as close as possible to VCC, grounded to the exposed PAD and ground pins. The VCC output pin must not be loaded, left floating, or shorted to ground during operation. Shorting VCC to ground during operation may cause damage to the LM46002-Q1.

Undervoltage lockout (UVLO) prevents the LM46002-Q1 from operating until the V_CC voltage exceeds 3.15 V (typical). The V_CC UVLO threshold has 575 mV of hysteresis (typically) to prevent undesired shutting down due to temporary V_IN droops.

The internal LDO has two inputs: primary from VIN and secondary from BIAS input. The BIAS input powers the LDO when V_BIAS is higher than the change-over threshold. Power loss of an LDO is calculated by I_LDO * (V_IN-LDO – V_OUT-LDO). The higher the difference between the input and output voltages of the LDO, the more power loss occur to supply the same output current. The BIAS input is designed to reduce the difference of the input and output voltages of the LDO to reduce power loss and improve LM46002-Q1 efficiency, especially at light load. TI recommends tying the BIAS pin to V_OUT when V_OUT ≥ 3.3V. Ground the BIAS pin in applications with V_OUT less than 3.3 V. BIAS input can also come from an external voltage source, if available, to reduce power loss. When used, a TI recommends a 1-µF to 10-µF high-quality ceramic capacitor to bypass the BIAS pin to ground.

7.3.6 Soft-Start and Voltage Tracking (SS/TRK)

The LM46002-Q1 has a flexible and easy-to-use start-up rate control pin: SS/TRK. Soft-start feature is to prevent inrush current impacting the LM46002-Q1 and its supply when power is first applied. Soft-start is achieved by slowly ramping up the target regulation voltage when the device is first enabled or powered up.

The simplest way to use the device is to leave the SS/TRK pin open circuit or floating. The LM46002-Q1 employs the internal soft-start control ramp and start-up to the regulated output voltage in 4.1 ms typically.

In applications with a large amount of output capacitors, higher V_OUT, or other special requirements, the soft-start time can be extended by connecting an external capacitor C_SS from SS/TRK pin to AGND. Extended soft-start time further reduces the supply current needed to charge up output capacitors and supply any output loading. An internal current source (I_SSC = 2.2 µA) charges C_SS and generates a ramp from 0 V to V_FB to control the ramp-up rate of the output voltage. For a desired soft-start time t_SS, the capacitance for C_SS can be found by

Equation 2.

The soft start capacitor C_SS is discharged by an internal FET when V_OUT is shutdown by hiccup protection or ENABLE = logic low. When a large C_SS is applied and ENABLE is toggled low only for a short period of time, the C_SS may not be fully discharged, and the next soft-start ramp will follow internal soft-start ramp before reaching the leftover voltage on C_SS, then follow the ramp programmed by C_SS. If this is not acceptable for a certain application, a R-C low-pass filter can be added to ENABLE to slow down the shutting down of VCC, which allows more time to discharge C_SS.

The LM46002-Q1 is capable of start-up into prebiased output conditions. When the inductor current reaches zero, the LS switch is turned off to avoid negative current conduction. This operation mode is also called diode emulation mode. It is built in by the DCM operation in light loads. With a prebiased output voltage, the LM46002-Q1 waits until the soft-start ramp allows regulation above the prebiased voltage and then follows the soft-start ramp to the regulation level.

When an external voltage ramp is applied to the SS/TRK pin, the LM46002-Q1 FB voltage follows the ramp if the ramp magnitude is lower than the internal soft-start ramp. A resistor divider pair can be used on the external control ramp to the SS/TRK pin to program the tracking rate of the output voltage. The final voltage detected by the SS/TRK pin must not fall below 1.2 V to avoid abnormal operation.

Figure 37. Soft Start Tracking External Ramp

V_OUT tracked to an external voltage ramp has the option of ramping up slower or faster than the internal voltage ramp. V_FB always follows the lower potential of the internal voltage ramp and the voltage on the SS/TRK pin. Figure 38 shows the case when V_OUT ramps slower than the internal ramp, while Figure 39 shows when V_OUT ramps faster than the internal ramp. Faster start up time may result in inductor current tripping current protection during start-up. Use with special care.

Figure 38. Tracking With Longer Start-up Time Than Tthe Internal Ramp

Figure 39. Tracking With Shorter Start-up Time Than the Internal Ramp

7.3.7 Switching Frequency (RT) and Synchronization (SYNC)

The switching frequency of the LM46002-Q1 can be programmed by the impedance R_T from the RT pin to ground. The frequency is inversely proportional to the R_T resistance. The RT pin can be left floating, and the LM46002-Q1 will operate at 500-kHz default switching frequency. The RT pin is not designed to be shorted to ground.

For a desired frequency, typical R_T resistance can be found by Equation 3.

Figure 40 shows R_T resistance vs switching frequency F_S curve.

Figure 40. R_T Resistance vs Switching Frequency

Table 1 provides typical R_T values for a given F_S.

The LM46002-Q1 switching action can also be synchronized to an external clock from 200 kHz to 2.2 MHz. Connect an external clock to the SYNC pin, with proper high speed termination, to avoid ringing. Ground the SYNC pin if not used.

Figure 41. Frequency Synchronization

The recommendations for the external clock include high level no lower than 2 V, low level no higher than 0.4 V, duty cycle between 10% and 90%, and both positive and negative pulse width no shorter than 80 ns. When the external clock fails at logic high or low, the LM46002-Q1 switches at the frequency programmed by the R_T resistor after a time-out period. TI recommends connecting a resistor R_T to the RT pin so that the internal oscillator frequency is the same as the target clock frequency when the LM46002-Q1 is synchronized to an external clock. This allows the regulator to continue operating at approximately the same switching frequency if the external clock fails.

The choice of switching frequency is usually a compromise between conversion efficiency and the size of the circuit. Lower switching frequency implies reduced switching losses (including gate charge losses, switch transition losses, etc.) and usually results in higher overall efficiency. However, higher switching frequency allows use of smaller LC output filters and hence a more compact design. Lower inductance also helps transient response (higher large signal slew rate of inductor current), and reduces the DCR loss. The optimal switching frequency is usually a trade-off in a given application and thus needs to be determined on a case-by-case basis. It is related to the input voltage, output voltage, most frequent load current level(s), external component choices, and circuit size requirement. The choice of switching frequency may also be limited if an operating condition triggers T_ON-MIN or T_OFF-MIN.

7.3.8 Minimum ON-Time, Minimum OFF-Time and Frequency Foldback at Dropout Conditions

Minimum ON-time, T_ON-MIN, is the smallest duration of time that the HS switch can be on. t_ON-MIN is typically 125 ns in the LM46002-Q1. Minimum OFF-time, t_OFF-MIN, is the smallest duration that the HS switch can be off. t_OFF-MIN is typically 200 ns in the LM46002-Q1.

In CCM operation, t_ON-MIN and t_OFF-MIN limits the voltage conversion range given a selected switching frequency. The minimum duty cycle allowed is

And the maximum duty cycle allowed is

Given fixed t_ON-MIN and t_OFF-MIN, the higher the switching frequency the narrower the range of the allowed duty cycle. In the LM46002-Q1, frequency foldback scheme is employed to extend the maximum duty cycle when t_OFF-MIN is reached. The switching frequency decreases once longer duty cycle is needed under low V_IN conditions. The switching frequency can be decreased to approximately 1/10 of the programmed frequency by R_T or the synchronization clock. Such a wide range of frequency foldback allows the LM46002-Q1 output voltage to stay in regulation with a much lower supply voltage V_IN. This leads to a lower effective dropout voltage. See Typical Characteristics for more details.

Given an output voltage, the choice of the switching frequency affects the allowed input voltage range, solution size and efficiency. The maximum operational supply voltage can be found by:

At lower supply voltage, the switching frequency decreases once t_OFF-MIN is tripped. The minimum V_IN without frequency foldback can be approximated by:

Taking considerations of power losses in the system with heavy load operation, V_IN-MIN is higher than the result calculated in Equation 7 . With frequency foldback, V_IN-MIN is lowered by decreased F_S. Figure 42 gives an example of how F_S decreases with decreasing supply voltage V_IN at dropout operation.

Figure 42. Switching Frequency Decreases in Dropout Operation
V_OUT = 5 V F_S = 1 MHz

7.3.9 Internal Compensation and C_FF

The LM46002-Q1 is internally compensated with R_C = 400 kΩ and C_C = 50 pF as shown in Functional Block Diagram. The internal compensation is designed such that the loop response is stable over the entire operating frequency and output voltage range. Depending on the output voltage, the compensation loop phase margin can be low with all ceramic capacitors. TI recommends an external feed-forward cap C_FF be placed in parallel with the top resistor divider R_FBT for optimum transient performance as shown in Figure 43.

Figure 43. Feed-Forward Capacitor for Loop Compensation

The feed-forward capacitor C_FF in parallel with R_FBT places an additional zero before the cross over frequency of the control loop to boost phase margin. The zero frequency can be found by

An additional pole is also introduced with C_FF at the frequency of

Select the C_FF so that the bandwidth of the control loop without the C_FF is centered between f_Z-CFF and f_P-CFF. The zero f_Z-CFF adds phase boost at the crossover frequency and improves transient response. The pole f_P-CFF helps maintaining proper gain margin at frequency beyond the crossover.

Designs with different combinations of output capacitors need different C_FF. Different types of capacitors have different equivalent series resistance (ESR). Ceramic capacitors have the smallest ESR and need the most C_FF. Electrolytic capacitors have much larger ESR than ceramic, and the ESR zero frequency location would be low enough to boost the phase up around the crossover frequency. Designs that use mostly electrolytic capacitors at the output may not need any CFF. The location of this ESR zero frequency can be calculated withEquation 10:

The C_FF creates a time constant with R_FBT that couples in the attenuated output voltage ripple to the FB node. If the C_FF value is too large, it can couple too much ripple to the FB and affect V_OUT regulation. It could also couple too much transient voltage deviation and falsely trip PGOOD thresholds. Therefore, C_FF should be calculated based on output capacitors used in the system. At cold temperatures, the value of C_FF might change based on the tolerance of the chosen component. This may reduce its impedance and ease noise coupling on the FB node. To avoid this, more capacitance can be added to the output or the value of C_FF can be reduced. See Detailed Design Procedure for the calculation of C_FF.

7.3.10 Bootstrap Voltage (BOOT)

The driver of the HS switch requires a bias voltage higher than V_IN when the HS switch is ON. The capacitor connected between CBOOT and SW pins works as a charge pump to boost voltage on the CBOOT pin to (V_SW + V_CC). The boot diode is integrated on the LM46002-Q1 die to minimize the bill of material (BOM). A synchronous switch is also integrated in parallel with the boot diode to reduce voltage drop on CBOOT. TI recommends a high-quality ceramic 0.47-µF, 6.3-V or higher capacitor for C_BOOT.

7.3.11 Power Good (PGOOD)

The LM46002-Q1 has a built-in power-good flag shown on PGOOD pin to indicate whether the output voltage is within its regulation level. The PGOOD signal can be used for start-up sequencing of multiple rails or fault protection. The PGOOD pin is an open-drain output that requires a pullup resistor to an appropriate DC voltage. Voltage seen by the PGOOD pin must never exceed 12 V. A resistor divider pair can be used to divide the voltage down from a higher potential. A typical range of pullup resistor value is 10 kΩ to 100 kΩ.

When the FB voltage is within the power-good band, +4% above and –7% below the internal reference V_REF typically, the PGOOD switch is turned off, and the PGOOD voltage is pulled up to the voltage level defined by the pullup resistor or divider. When the FB voltage is outside of the tolerance band, +10 % above or –13 % below V_REF typically, the PGOOD switchis turned on, and the PGOOD pin voltage is pulled low to indicate power bad. Both rising and falling edges of the power-good flag have a built-in 220-µs (typical) deglitch delay.

7.3.12 Overcurrent and Short-Circuit Protection

The LM46002-Q1 is protected from overcurrent conditions by cycle-by-cycle current limiting on both peak and valley of the inductor current. Hiccup modeis activated if a fault condition persists to prevent overheating.

High-side MOSFET overcurrent protection is implemented by the nature of the peak current mode control. The HS switch current is sensed when the HS is turned on after a set blanking time. The HS switch current is compared to the output of the error amplifier (EA) minus slope compensation every switching cycle. See the Functional Block Diagram for more details. The peak current of the HS switch is limited by the maximum EA output voltage minus the slope compensation at every switching cycle. The slope compensation magnitude at the peak current is proportional to the duty cycle.

When the LS switch is turned on, the current going through it is also sensed and monitored. The LS switch is be turned OFF at the end of a switching cycle if its current is above the LS current limit I_LS-LIMIT. The LS switch is kept ON so that inductor current keeps ramping down, until the inductor current ramps below I_LS-LIMIT. The LS switch is then turned OFF, and the HS switch is turned on after a dead time. If the current of the LS switch is higher than the LS current limit for 32 consecutive cycles and the power-good flag is low, hiccup-current-protection mode is activated. In hiccup mode, the regulator is shut down and kept off for 5.5 ms typically before the LM46002-Q1 tries to start again. If overcurrent or short-circuit fault condition still exist, hiccup repeats until the fault condition is removed. Hiccup mode reduces power dissipation under severe overcurrent conditions, prevents overheating and potential damage to the device.

Hiccup is only activated when power-good flag is low. Under non-severe overcurrent conditions when V_OUT has not fallen outside of the PGOOD tolerance band, the LM46002-Q1 reduces the switching frequency and keeps the inductor current valley clamped at the LS current limit level. This operation mode allows slight overcurrent operation during load transients without tripping hiccup. If the power-good flag becomes low, hiccup operation starts after LS current limit is tripped 32 consecutive cycles.

7.3.13 Thermal Shutdown

Thermal shutdown is a built-in self protection to limit junction temperature and prevent damages due to over heating. Thermal shutdown turns off the device when the junction temperature exceeds 160°C typically to prevent further power dissipation and temperature rise. Junction temperature will reduce after thermal shutdown. The LM46002-Q1 attempts to restart when the junction temperature drops to 150°C.

7.4.1 Shutdown Mode

The EN pin provides electrical ON and OFF control for the LM46002-Q1. When V_EN is below 0.4 V, the device is in shutdown mode. Both the internal LDO and the switching regulator are off. In shutdown mode the quiescent current drops to 2.3 µA typically with V_IN = 24 V. The LM46002-Q1 also employs UVLO protection. If V_CC voltage is below the UVLO level, the output of the regulator is turned off.

7.4.2 Stand-by Mode

The internal LDO has a lower enable threshold than the regulator. When V_EN is above 1.2 V and below the precision-enable falling threshold (1.8 V typically), the internal LDO regulates the V_CC voltage at 3.2 V. The precision-enable circuitry is turned on once V_CC is above the UVLO threshold. The switching action and voltage regulation are not enabled unless V_EN rises above the precision enable threshold (2.1 V typically).

7.4.3 Active Mode

The LM46002-Q1 is in active mode when V_EN is above the precision enable threshold and V_CC is above its UVLO level. The simplest way to enable the LM46002-Q1 is to connect the EN pin to V_IN. This allows self start-up when the input voltage is in the operation range: 3.5 V to 60 V. See Enable (ENABLE) and VCC, UVLO and BIAS for details on setting these operating levels.

In active mode, depending on the load current, the LM46002-Q1 is in one of four modes:

1. CCM with fixed switching frequency when load current is above half of the peak-to-peak inductor current ripple;
2. DCM with fixed switching frequency when load current is lower than half of the peak-to-peak inductor current ripple in CCM operation;
3. PFM when switching frequency is decreased at very light load;
4. Foldback mode when switching frequency is decreased to maintain output regulation at lower supply voltage V_IN.

7.4.4 CCM Mode

Continuous conduction mode (CCM) operation is employed in the LM46002-Q1 when the load current is higher than half of the peak-to-peak inductor current. In CCM operation, the frequency of operation is fixed unless the minimum HS switch ON-time (t_ON-MIN), the minimum HS switch OFF-time (t_ON-MAX) or LS current limit is exceeded. Output voltage ripple is at a minimum in this mode and the maximum output current of 2 A can be supplied by the LM46002-Q1.

7.4.5 Light Load Operation

When the load current is lower than half of the peak-to-peak inductor current in CCM, the LM46002-Q1 operate in discontinuous conduction mode (DCM), also known as diode emulation mode (DEM). In DCM operation, the LS FET is turned off when the inductor current drops to 0 A to improve efficiency. Both switching losses and conduction losses are reduced in DCM, comparing to forced PWM operation at light load.

At even lighter current loads, PFM is activated to maintain high efficiency operation. When the HS switch ON-time reduces to t_ON-MIN or peak inductor current reduces to its minimum I_PEAK-MIN, the switching frequency reduces to maintain proper regulation. Efficiency is greatly improved by reducing switching and gate drive losses.

7.4.6 Self-Bias Mode

For highest efficiency of operation, it is recommended that the BIAS pin be connected directly to V_OUT when 3.3 V ≤ V_OUT ≤ 28 V. In this self-bias mode of operation, the difference between the input and output voltages of the internal LDO are reduced, and therefore the total efficiency is improved. These efficiency gains are more evident during light load operation. During this mode of operation, the LM46002-Q1 operates with a minimum quiescent current of 27 µA (typical). See VCC, UVLO and BIAS for more details.