7.3.1 High-Voltage Start-Up Regulator

The LM5005 contains a dual-mode internal high-voltage start-up regulator that provides the VCC bias supply for the PWM controller and bootstrap MOSFET gate driver. The VIN pins can be connected directly to the input voltage, as high as 75 V. For input voltages below 9 V, a low dropout switch connects VCC directly to VIN. In this supply range, VCC is approximately equal to VIN. For input voltages greater than 9 V, the low dropout switch is disabled and the VCC regulator is enabled to maintain VCC at approximately 7 V. The wide operating range of
7 V to 75 V is achieved through the use of this dual-mode regulator.

The output of the VCC regulator is current limited to 20 mA. Upon power up, the regulator sources current into the capacitor connected to the VCC pin. When the voltage at the VCC pin exceeds the VCC UVLO threshold of 6.3 V and the SD pin is greater than 1.225 V, a soft-start sequence begins. Switching continues until VCC falls below 5.3 V or the SD pin falls below 1.125 V.

An auxiliary supply voltage can be applied to the VCC pin to reduce the IC power dissipation. If the auxiliary voltage is greater than 7.3 V, the internal regulator essentially shuts off, reducing the IC power dissipation. The VCC regulator series pass transistor includes a diode between VCC and VIN that must not be forward biased in normal operation. Therefore the auxiliary VCC voltage must never exceed the VIN voltage.

Take extra care in high-voltage applications to ensure the VIN and PRE pin voltages do not exceed their absolute maximum voltage ratings of 76 V. During line or load transients, voltage ringing on the input bus that exceeds the Absolute Maximum Ratings can damage the IC. Careful PC board layout and the use of quality input bypass capacitors placed close to the VIN and PGND pins are essential. See Layout Guidelines for more detail.

Figure 8. VIN and VCC Sequencing

7.3.2 Shutdown and Standby

The LM5005 contains a dual-level shutdown (SD) circuit. When the SD pin voltage is below 0.7 V, the regulator is in a low-current shutdown mode. When the SD pin voltage is greater than 0.7 V but less than 1.225 V, the regulator is in standby mode. In standby mode the VCC regulator is active but MOSFET switching is disabled. When the SD pin voltage exceeds 1.225 V, switching is enabled and normal operation begins. An internal 5-µA pullup current source configures the regulator to be fully operational if the SD pin is left open.

An external voltage divider from VIN to GND can be used to set the operational input range of the regulator. The divider must be designed such that the voltage at the SD pin is greater than 1.225 V when VIN is in the desired operating range. The internal 5-µA pullup current source must be included in calculations of the external set-point divider. Hysteresis of 0.1 V is included for both the shutdown and standby thresholds. The voltage at the SD pin must never exceed 7 V. When using an external divider, it may be necessary to clamp the SD pin to limit its voltage at high input voltage conditions.

7.3.3 Oscillator and Synchronization Capability

The LM5005 oscillator frequency is set by a single external resistor designated R_T connected between the RT and AGND pins. Place the R_T resistor close to the LM5005's RT and AGND pins. Calculate the resistance of R_T from Equation 1 to set a desired switching frequency, F_SW.

Equation 1.

The SYNC pin can be used to synchronize the internal oscillator to an external clock. The external clock signal must be of higher frequency than the free-running frequency of the LM5005 set by the R_T resistor. A clock circuit with an open-drain output as shown in Figure 9 is the recommended interface to the SYNC pin. The clock pulse duration must be greater than 15 ns.

Figure 9. External Clock Synchronization

Figure 10. Self-Synchronization of Multiple
LM5005 Regulators

Multiple LM5005 devices can be synchronized together simply by connecting the SYNC pins together. In this configuration all of the devices are synchronized to the highest frequency device. The diagram in Figure 11 illustrates the SYNC input/output features of the LM5005. The internal oscillator circuit drives the SYNC pin with a strong pulldown and weak pullup inverter. When the SYNC pin is pulled low either by the internal oscillator or an external clock, the ramp cycle of the oscillator is terminated and a new oscillator cycle begins. Thus, if the SYNC pins of several LM5005 IC's are connected together, the IC with the highest internal clock frequency pulls the connected SYNC pins low first and terminates the oscillator ramp cycles of the other IC’s. The LM5005 with the highest programmed clock frequency serves as the master and controls the switching frequency of all the devices with lower oscillator frequency.

Figure 11. Simplified Oscillator Block Diagram and SYNC I/O Circuit

7.3.4 Error Amplifier and PWM Comparator

The internal high-gain error amplifier generates an error signal proportional to the difference between the regulated output voltage and an internal precision reference of 1.225 V. The output of the error amplifier is at the COMP pin, allowing the user to connect loop compensation components, generally a type-II network, from COMP to FB as illustrated in the Functional Block Diagram. This network creates a pole at unity frequency, a zero, and a noise-attenuating high-frequency pole. The PWM comparator compares the emulated current sense signal from the RAMP generator to the error amplifier's output voltage at the COMP pin.

7.3.5 RAMP Generator

The ramp signal used in the pulse width modulator for current-mode control is typically derived directly from the buck switch current. This switch current corresponds to the positive slope portion of the output inductor current. Using this signal for the PWM ramp simplifies the control loop transfer function to a single pole response and provides inherent input voltage feedforward compensation. The disadvantage of using the buck switch current signal for PWM control is the large leading-edge spike due to circuit parasitics that must be filtered or blanked. Also, the current measurement may introduce significant propagation delays. The filtering, blanking time and propagation delay limit the minimum achievable pulse-width. In applications where the input voltage may be relatively large in comparison to the output voltage, controlling small pulse-widths and duty cycles is necessary for regulation. The LM5005 uses a unique ramp generator, which does not actually measure the buck switch current but rather reconstructs the current signal. Reconstructing or emulating the inductor current provides a ramp signal to the PWM comparator that is free of leading-edge spikes and measurement or filtering delays. The current reconstruction is comprised of two elements: a sample-and-hold DC level and an emulated current ramp.

Figure 12. Emulated Current-Sense Ramp Waveform

The sample-and-hold DC level illustrated in Figure 12 is derived from a measurement of the current flowing in the freewheeling Schottky diode. Connect the freewheeling diode's anode terminal to the LM5005's IS pin. The diode current flows through an internal current sense resistor between the IS and PGND pins. The voltage level across the sense resistor is sampled and held just prior to the onset of the next conduction interval of the buck switch. The diode current sensing and sample-and-hold provide the DC level for the reconstructed current signal. The positive slope inductor current ramp is emulated by an internal voltage-controlled current source and an external capacitor connected between the RAMP and AGND pins. The ramp current source that emulates the inductor current is a function of the input and output voltages given by Equation 2.

Equation 2.

Proper selection of the RAMP capacitor depends upon the selected output inductance. Select the capacitance of C_RAMP using Equation 3.

Equation 3.

where

• L_F is the output inductance in Henrys

With this value, the scale factor of the emulated current ramp is approximately equal to the scale factor of the DC level sample-and-hold (0.5 V/A). Place the C_RAMP capacitor close to the LM5005's RAMP and AGND pins.

For duty cycles greater than 50%, peak current-mode control circuits are subject to subharmonic oscillation. Subharmonic oscillation is normally characterized by observing alternating wide and narrow pulses of the switch-node voltage waveform. Adding a fixed-slope voltage ramp (slope compensation) to the current sense signal prevents this oscillation. The 25 µA of offset current provided from the emulated current source adds some fixed slope to the ramp signal. In some high output voltage and high duty cycle applications, additional slope may be required. In these applications, add a pullup resistor between the VCC and RAMP pins to increase the ramp slope compensation.

For V_OUT > 7.5 V, calculate the optimal slope current with Equation 4.

For example, at V_OUT = 10 V, I_OS = 50 µA.

Install a resistor from the RAMP pin to VCC using Equation 5.

Figure 13. Connection of External Ramp Resistor to VCC when V_OUT > 7.5 V

7.3.6 Current Limit

The LM5005 contains a unique current monitoring scheme for control and overcurrent protection. When set correctly, the emulated current sense signal provides a signal that is proportional to the buck switch current with a scale factor of 0.5 V/A. The emulated ramp signal is applied to the current limit comparator. If the emulated ramp signal exceeds 1.75 V (3.5 A), the present cycle is terminated (cycle-by-cycle current limiting). In applications with small output inductance and high input voltage, the switch current may overshoot due to the propagation delay of the current limit comparator. If an overshoot must occur, the diode current sampling circuit detects the excess inductor current during the off-time of the buck switch. If the sample-and-hold DC level exceeds the 1.75-V current limit threshold, the buck switch is disabled and skip pulses until the diode current sampling circuit detects that the inductor current has decayed below the current limit threshold. This approach prevents current runaway conditions due to propagation delays or inductor saturation, because the inductor current is forced to decay following any current overshoot.

7.3.7 Soft-Start Capability

The soft-start feature prevents inrush current impacting the LM5005 regulator and the input supply when power is first applied. Output voltage soft-start is achieved by slowly ramping up the target regulation voltage when the device is first enabled or powered up. The internal soft-start current source of 10 µA gradually increases the voltage of an external soft-start capacitor connected to the SS pin. The soft-start capacitor voltage is connected to the noninverting input of the error amplifier. Various sequencing and tracking schemes can be implemented using external circuits that limit or clamp the voltage level of the SS pin.

In the event a fault is detected, including overtemperature, VCC UVLO or shutdown, the soft-start capacitor is discharged. When the fault condition is no longer present, a new soft-start sequence commences.

7.3.8 MOSFET Gate Driver

The LM5005 integrates an N-channel high-side MOSFET and associated floating high-voltage gate driver. This gate driver circuit works in conjunction with an internal bootstrap diode and an external bootstrap capacitor. A
22-nF ceramic capacitor, connected with short traces between the BST and SW pins, is recommended. During the off time of the buck switch, the SW voltage is approximately –0.5 V and the bootstrap capacitor is charged from VCC through the internal bootstrap diode. When operating at a high PWM duty cycle, the buck switch is forced off each cycle for 500 ns to ensure that the bootstrap capacitor is recharged.

Under light-load conditions or when the output voltage is precharged, the SW voltage may not remain low during the off-time of the buck switch. If the inductor current falls to zero and the SW voltage rises, the bootstrap capacitor may not have sufficient voltage to operate the buck switch gate driver. For these applications, connect the PRE pin to the SW pins to precharge the bootstrap capacitor. The internal precharge MOSFET and diode connected between the PRE and PGND pins turns on each cycle for 250 ns just prior to the onset of a new switching cycle. If the SW pin is at a normal negative voltage level (continuous conduction mode), then no current flows through the precharge MOSFET and diode.

7.4.1 Shutdown Mode

The SD pin provides ON and OFF control for the LM5005. When V_SD is below approximately 0.6 V, the device is in shutdown mode. Both the internal LDO and the switching regulator are off. The quiescent current in shutdown mode drops to 60 µA at V_IN = 48 V. The LM5005 also employs VCC bias rail undervoltage protection. If the VCC bias supply voltage is below its UV threshold, the regulator remains off.

7.4.2 Standby Mode

The bias supply subregulator has a lower enable threshold than the regulator itself. When V_SD is above 0.6 V and below the standby threshold (1.225 V typically), the VCC supply is on and regulating. Switching action and output voltage regulation are not enabled until V_SD rises above the standby threshold.

7.4.3 Light-Load Operation

The LM5005 maintains high efficiency when operating at light loads. Whenever the load current is reduced to a level less than half the peak-to-peak inductor ripple current, the device enters discontinuous conduction mode (DCM). Calculate the critical conduction boundary using Equation 6.

Equation 6.

When the inductor current reaches zero, the SW node becomes high impedance. Resonant ringing occurs at SW as a result of the LC tank circuit formed by the buck inductor and the parasitic capacitance at the SW node. At light loads, typically below 100 mA, several pulses may be skipped in between switching cycles, effectively reducing the switching frequency and further improving light-load efficiency.

7.4.4 Thermal Shutdown Protection

Internal thermal shutdown circuitry is provided to protect the regulator in the event that the maximum junction temperature is exceeded. When activated, typically at 165°C, the regulator is forced into a low power reset state, disabling the output driver and the bias regulator. This feature is provided to prevent catastrophic failures from accidental device overheating.