10.1.1 PCB Layout for EMI Reduction

Radiated EMI generated by high slew-rate current edges relates to pulsating currents in switching converters. The larger area covered by the path of a pulsing current, the more electromagnetic emission is generated. The key to reducing radiated EMI is to identify the pulsing current path and minimize the area of that path.

The important high-frequency switching power loop (or hot loop) of the LM5005 power stage is denoted in blue in Figure 34. The topological architecture of a buck converter means that particularly high di/dt current exists in this loop as current commutates between the externally-connected Schottky diode and the integrated high-side MOSFET during switching transitions. As such, it becomes mandatory to minimize this effective loop area, with an eye to reducing the layout-induced parasitic or stray inductances that cause excessive SW voltage overshoot and ringing, noise and ground bounce.

In general, MOSFET switching behavior and the consequences for waveform ringing, power dissipation, device stress and EMI are correlated with the parasitic inductances of the power loop. It follows that the cumulative benefits of reducing the switching loop area are increased reliability and robustness owing to lower power MOSFET voltage and current stress, increased margin for input voltage transients, and easier EMI filtering (particularly in the more challenging high-frequency band above 30 MHz).

Figure 34. LM5005 Power Stage Circuit Switching Loops

High-frequency ceramic bypass capacitors at the input side provide the primary path for the high di/dt components of the pulsing current. Position low-ESL ceramic bypass capacitors with low-inductance, short trace routes to the VIN and PGND pins. Keep the SW trace connecting to the inductor as short as possible, and just wide enough to carry the load current without excessive heating. Use short, thick traces or copper polygon pours (shapes) for current conduction paths to minimize parasitic resistance. Place the output capacitors close to the VOUT side of the inductor and route the return connection using GND plane copper back to the PGND pins and the exposed pad of the LM5005.

10.1.2 Thermal Design

As with any power conversion device, the LM5005 dissipates internal power while operating. The effect of this power dissipation is to raise the internal junction temperature of the LM5005 above ambient. The junction temperature (T_J) is a function of the ambient temperature (T_A), the power dissipation (P_D) and the effective thermal resistance of the device and PCB combination (R_θJA). The maximum operating junction temperature for the LM5005 is 125°C, thus establishing a limit on the maximum device power dissipation and therefore the load current at high ambient temperatures. Equation 21 and Equation 22 show the relationships between these parameters.

Equation 21.

Equation 22.

An approximation for the inductor power loss in Equation 21 includes a factor of 1.5 for the core losses. Also, if a snubber is used, estimate its power loss by observation of the resistor voltage drop at both turnon and turnoff switching transitions.

High ambient temperatures and large values of R_θJA reduce the maximum available output current. If the junction temperature exceeds 165°C, the LM5005 cycles in and out of thermal shutdown. Thermal shutdown may be a sign of inadequate heat-sinking or excessive power dissipation. Improve PCB heat-sinking by using more thermal vias, a larger board, or more heat-spreading layers within that board.

As stated in Semiconductor and IC Package Thermal Metrics (SPRA953), the values given in Thermal Information are not always valid for design purposes to estimate the thermal performance of the application. The values reported in this table are measured under a specific set of conditions that are seldom obtained in an actual application. The effective R_θJA is a critical parameter and depends on many factors (such as power dissipation, air temperature, PCB area, copper heat-sink area, number of thermal vias under the package, air flow, and adjacent component placement). The LM5005's exposed pad has a direct thermal connection to PGND. This pad must be soldered directly to the PCB copper ground plane to provide an effective heat-sink and proper electrical connection. Use the documents listed in Documentation Support as a guide for optimized thermal PCB design and estimating R_θJA for a given application environment.

10.1.3 Ground Plane Design

As mentioned previously, using one of the inner PCB layers as a solid ground plane is recommended. A ground plane offers shielding for sensitive circuits and traces and also provides a quiet reference potential for the control circuitry. Connect the PGND pins to the system ground plane using an array of vias under the LM5005's exposed pad. Also connect the PGND pins directly to the return terminals of the input and output capacitors. The PGND net contains noise at the switching frequency and can bounce because of load current variations. The power traces for PGND, VIN, and SW can be restricted to one side of the ground plane. The other side of the ground plane contains much less noise and is ideal for sensitive analog trace routes.