SNVS397E September   2005  – November 2016 LM5005

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 High-Voltage Start-Up Regulator
      2. 7.3.2 Shutdown and Standby
      3. 7.3.3 Oscillator and Synchronization Capability
      4. 7.3.4 Error Amplifier and PWM Comparator
      5. 7.3.5 RAMP Generator
      6. 7.3.6 Current Limit
      7. 7.3.7 Soft-Start Capability
      8. 7.3.8 MOSFET Gate Driver
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Standby Mode
      3. 7.4.3 Light-Load Operation
      4. 7.4.4 Thermal Shutdown Protection
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Reducing Bias Power Dissipation
      2. 8.1.2 Input Voltage UVLO Protection
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Frequency Set Resistor (RT)
        2. 8.2.2.2  Inductor (LF)
        3. 8.2.2.3  Ramp Capacitor (CRAMP)
        4. 8.2.2.4  Output Capacitors (COUT)
        5. 8.2.2.5  Schottky Diode (DF)
        6. 8.2.2.6  Input Capacitors (CIN)
        7. 8.2.2.7  VCC Capacitor (CVCC)
        8. 8.2.2.8  Bootstrap Capacitor (CBST)
        9. 8.2.2.9  Soft Start Capacitor (CSS)
        10. 8.2.2.10 Feedback Resistors (RFB1 and RFB2)
        11. 8.2.2.11 RC Snubber (RS and CS)
        12. 8.2.2.12 Compensation Components (RC1, CC1, CC2)
        13. 8.2.2.13 Bill of Materials
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 PCB Layout for EMI Reduction
      2. 10.1.2 Thermal Design
      3. 10.1.3 Ground Plane Design
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Third-Party Products Disclaimer
    2. 11.2 Device Support
      1. 11.2.1 Development Support
    3. 11.3 Documentation Support
      1. 11.3.1 Related Documentation
        1. 11.3.1.1 PCB Layout Resources
        2. 11.3.1.2 Thermal Design Resources
    4. 11.4 Receiving Notification of Documentation Updates
    5. 11.5 Community Resources
    6. 11.6 Trademarks
    7. 11.7 Electrostatic Discharge Caution
    8. 11.8 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted)(1)(2)
MIN MAX UNIT
VIN to GND 76 V
BST to GND 90 V
PRE to GND 76 V
SW to GND (steady state) –1.5 76 V
BST to VCC 76 V
VCC to GND 14 V
BST to SW 14 V
OUT to GND Limited to VVIN V
SD, SYNC, SS, FB to GND 7 V
Junction temperature, TJ –40 150 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±750
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VIN Input voltage 7 75 V
IOUT Output current 0 2.5 A
TJ Operating junction temperature –40 125 °C
(1) Recommended Operating Conditions are conditions under which operation of the device is intended to be functional. For ensured specifications and test conditions, see the Electrical Characteristics.

6.4 Thermal Information

THERMAL METRIC(1) LM5005 UNIT
PWP (HTSSOP)
20 PINS
RθJA Junction-to-ambient thermal resistance 35.2 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 17.8 °C/W
RθJB Junction-to-board thermal resistance 15.5 °C/W
ψJT Junction-to-top characterization parameter 0.4 °C/W
ψJB Junction-to-board characterization parameter 15.3 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 1.2 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

Typical values correspond to TJ = 25°C. Minimum and maximum limits apply over the –40°C to 125°C junction temperature range. VIN = 48 V and RT = 32.4 kΩ (unless otherwise noted).(2)
PARAMETER TEST CONDITIONS MIN(1) TYP MAX(1) UNIT
START-UP REGULATOR
VVCC-REG VCC regulator output 6.85 7.15 7.45 V
VVCC-EXT VCC LDO mode turnoff 9 V
IVCC-CL VCC current limit VVCC = 0 V 20 mA
VCC SUPPLY
VVCC-UV VCC UVLO threshold VVCC increasing 5.95 6.35 6.75 V
VVCC-HYS VCC undervoltage hysteresis 1 V
IVCC Bias current, IIN VFB = 1.3 V 5 mA
ISD Shutdown current, IIN VSD = 0 V 60 100 µA
SHUTDOWN THRESHOLDS
VSD-TH Shutdown threshold 0.5 0.7 0.9 V
VSD-HYS Shutdown hysteresis 0.1 V
VSBY-TH Standby threshold 1.18 1.225 1.27 V
VSBY-HYS Standby hysteresis 0.1 V
ISD SD pullup current source 5 µA
BUCK SWITCH
RDS-ON Buck switch, RDS(on) 160 320 mΩ
VBST-UV BOOST UVLO 3.8 V
VBST-UV-HYS BOOST UVLO hysteresis 0.56 V
RPRE Precharge switch, RDS(on) 75 Ω
CURRENT LIMIT
ICL Cycle-by-cycle current limit RAMP = 0 V 3 3.5 4.25 A
TCL-DLY Cycle-by-cycle current limit delay RAMP = 2.5 V 100 ns
SOFT-START
ISS SS current source 7 10 13 µA
OSCILLATOR
FSW1 Switching frequency 1 180 200 220 kHz
FSW2 Switching frequency 2 RT = 11 kΩ 425 485 525 kHz
RSYNC-SRC SYNC source impedance 10 kΩ
RSYNC-SINK SYNC sink impedance 160 Ω
VSYNC-FALL SYNC threshold (falling) 1.4 V
FSYNC-MAX SYNC frequency 550 kHz
TSYNC-MIN SYNC pulse width minimum 15 ns
RAMP GENERATOR
IRAMP1 Ramp current 1 VIN = 60 V, VOUT = 10 V 234 275 316 µA
IRAMP2 Ramp current 2 VIN = 10 V, VOUT = 10 V 20 25 30 µA
PWM COMPARATOR
VCOMP-OFS COMP to PWM comparator offset 0.7 V
ERROR AMPLIFIER
VFB Feedback voltage VFB = VCOMP 1.207 1.225 1.243 V
IFB-BIAS FB bias current 10 nA
AOL DC gain 70 dB
ICOMP COMP sink and source current 3 mA
FBW Unity gain bandwidth 3 MHz
THERMAL SHUTDOWN
TSD Thermal shutdown threshold 165 °C
TSD-HYS Thermal shutdown hysteresis 25 °C
(1) Minimum and maximum limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).
(2) The junction temperature (TJ in °C) is calculated from the ambient temperature (TA in °C) and power dissipation (PD in Watts) as follows: TJ = TA + (PD × RθJA) where RθJA (in °C/W) is the package thermal impedance provided in Thermal Information.

6.6 Switching Characteristics

Over operating free-air temperature range (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TON-MIN Minimum controllable PWM on-time 80 ns
TOFF-MIN Forced PWM off-time 500 ns
TPRE Precharge switch on-time 275 ns

6.7 Typical Characteristics

Unless otherwise specified, VIN = 48 V and VOUT = 5 V (see Typical Application for circuit designs).
LM5005 20161920.gif
Figure 1. Oscillator Frequency vs RT
LM5005 20161921.gif
FOSC = 200 kHz
Figure 2. Oscillator Frequency
vs Temperature
LM5005 20161922.gif
Figure 3. Soft-Start Current vs Temperature
LM5005 20161924.gif
RL = 7 kΩ
Figure 5. VCC vs VIN
LM5005 D001SNVS397E.gif Figure 7. LM5005 Evaluation Board Efficiency vs IOUT and VIN
LM5005 20161923.gif
VIN = 12 V
Figure 4. VCC vs ICC
LM5005 20161925.gif
AVCL = 101
Figure 6. Error Amplifier Gain and Phase