SNVSCA9
October 2022
LM5012
PRODUCTION DATA
1
Features
2
Applications
3
Description
4
Revision History
5
Device Comparison Table
6
Pin Configuration and Functions
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings_Catalog
7.3
Recommended Operating Conditions
7.4
Thermal Information
7.5
Electrical Characteristics
7.6
Typical Characteristics
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Control Architecture
8.3.2
Internal VCC Regulator and Bootstrap Capacitor
8.3.3
Regulation Comparator
8.3.4
Internal Soft Start
8.3.5
On-Time Generator
8.3.6
Current Limit
8.3.7
N-Channel Buck Switch and Driver
8.3.8
Schottky Diode Selection
8.3.9
Enable and Undervoltage Lockout (EN/UVLO)
8.3.10
Power Good (PGOOD)
8.3.11
Thermal Protection
8.4
Device Functional Modes
8.4.1
Shutdown Mode
8.4.2
Standby Mode
8.4.3
Active Mode
8.4.4
Sleep Mode
9
Application and Implementation
9.1
Application Information
9.2
Typical Application
9.2.1
Design Requirements
9.2.2
Detailed Design Procedure
9.2.2.1
Custom Design With WEBENCH® Tools
9.2.2.2
Switching Frequency (RRON)
9.2.2.3
Buck Inductor (LO)
9.2.2.4
Schottky Diode (DSW)
9.2.2.5
Output Capacitor (COUT)
9.2.2.6
Input Capacitor (CIN)
9.2.2.7
Type 3 Ripple Network
9.2.3
Application Curves
9.3
Power Supply Recommendations
9.4
Layout
9.4.1
Layout Guidelines
9.4.1.1
Compact PCB Layout for EMI Reduction
9.4.1.2
Feedback Resistors
9.4.2
Layout Example
9.4.2.1
Thermal Considerations
10
Device and Documentation Support
10.1
Device Support
10.1.1
Third-Party Products Disclaimer
10.1.2
Development Support
10.1.2.1
Custom Design With WEBENCH® Tools
10.2
Documentation Support
10.2.1
Related Documentation
10.3
Receiving Notification of Documentation Updates
10.4
Support Resources
10.5
Trademarks
10.6
Electrostatic Discharge Caution
10.7
Glossary
11
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
DDA|8
MPDS092F
Thermal pad, mechanical data (Package|Pins)
DDA|8
PPTD058I
Orderable Information
snvsca9_oa
9.2.2
Detailed Design Procedure