SNVS783K January 2012 – August 2021 LM5017
PRODUCTION DATA
Input capacitor should be large enough to limit the input voltage ripple as shown in Equation 17.
Choosing a ΔVIN = 0.5 V gives a minimum CIN = 1.3 μF. A standard value of 2.2 μF is selected for CIN = C4. The input capacitor should be rated for the maximum input voltage under all conditions. A 100-V, X7R dielectric should be selected for this design.
The input capacitor should be placed directly across VIN and RTN (pin 1 and 2) of the IC. If it is not possible to place all of the input capacitor close to the IC, a 0.47-μF capacitor should be placed near the IC to provide a bypass path for the high frequency component of the switching current.