10.1.1 Filter Capacitors

The low-value ceramic filter capacitors are most effective when the inductance of the current loops that they filter, is minimized. Place C_INX as close as possible to the VIN and GND pins of the LM5022-Q1. Place C_OX close to the load, and C_F next to the VCC and GND pins of the LM5022-Q1.

10.1.2 Sense Lines

The top of R_SNS should be connected to the CS pin with a separate trace, made as short as possible. Route this trace away from the inductor and the switch node (where D1, Q1, and L1 connect). For the voltage loop, keep R_FB1and R_FB2 close to the LM5022-Q1 and run a trace, as close as possible, to the positive side of C_OX to R_FB2. As with the CS line, the FB line should be routed away from the inductor and the switch node. These measures minimize the length of high impedance lines and reduce noise pickup.

10.1.3 Compact Layout

1. Parasitic inductance can be reduced by keeping the power path components close together. As described above in point 4 in the Layout Guidelines, keep the high slew-rate current loops as tight as possible. Short, thick traces or copper pours (shapes) are best
2. The switch node should be just large enough to connect all the components together without excessive heating from the current it carries. The LM5022-Q1 (boost converter) operates in two distinct cycles whose high current paths are shown in Figure 30:

Figure 30. Boost Converter Current Loops

The dark grey, inner loops represent the high current paths during the MOSFET on-time. The light grey, outer loop represents the high current path during the off-time.

10.1.4 Ground Plane and Shape Routing

The diagram of Figure 30 is useful for analyzing the flow of continuous current vs. the flow of pulsating currents. The circuit paths with current flow during both the on-time and off-time are considered to be continuous current, while those that carry current during the on-time or off-time only are pulsating currents. Preference in routing should be given to the pulsating current paths, as these are the portions of the circuit most likely to emit EMI. The ground plane of a PCB is a conductor and return path, and it is susceptible to noise injection just as any other circuit path. The continuous current paths on the ground net can be routed on the system ground plane with less risk of injecting noise into other circuits. The path between the input source, input capacitor and the MOSFET and the path between the output capacitor and the load are examples of continuous current paths. In contrast, the path between the grounded side of the power switch and the negative output capacitor terminal carries a large high slew-rate pulsating current. This path should be routed with a short, thick shape, preferably on the component side of the PCB. Too keep the parasitic inductance low, multiple vias in parallel should be placed on the negative pads of the input and output capacitors to connect the component side to the ground plane. Vias should not be placed directly at the grounded side of the MOSFET (or R_SNS) as they tend to inject noise into the ground plane. A second pulsating current loop is the gate drive loop formed by the OUT and VCC pins, Q1, R_SNS and capacitor C_F. These loops must be kept small.