The LM5025 PWM controller contains all of the features necessary to implement power converters using the active clamp reset technique. The device can be configured to control either a P-channel clamp switch or an
N-channel clamp switch. With the active clamp technique higher efficiencies and greater power densities can be realized compared to conventional catch winding or RDC clamp and reset techniques. Two control outputs are provided, the main power switch control (OUT_A), and the active clamp switch control (OUT_B). The active clamp output can be configured for either a specified overlap time (for P-channel switch applications) or a specified dead time (for N_channel applications). The two internal compound gate drivers parallel both MOS and bipolar devices, providing superior gate-drive characteristics. This controller is designed for high-speed operation including an oscillator frequency range up to 1 MHz and total PWM and current sense propagation delays less than 100 ns. The LM5025 includes a high-voltage start-up regulator that operates over a wide input of
13 V to 90 V. Additional features include: line undervoltage lockout (UVLO), soft-start, oscillator UP and DOWN sync capability, precision reference and thermal shutdown.

7.3.1 High-Voltage Start-Up Regulator

The LM5025 contains an internal high-voltage start-up regulator that allows the input pin (V_IN) to be connected directly to the line voltage. The regulator output is internally current limited to 20 mA. When power is applied, the regulator is enabled and sources current into an external capacitor connected to the V_CC pin. The recommended capacitance for the V_CC regulator is 0.1 µF to 100 µF. When the voltage on the V_CC pin reaches the regulation point of 7.6 V and the internal voltage reference (REF) reaches its regulation point of 5 V, the controller outputs are enabled. The outputs remains enabled until V_CC falls below 6.2 V or the line undervoltage lock out detector indicates that V_IN is out of range. In typical applications, an auxiliary transformer winding is connected through a diode to the V_CC pin. This winding must raise the V_CC voltage above 8 V to shut off the internal start-up regulator. Powering V_CC from an auxiliary winding improves efficiency while reducing the controller power dissipation.

The external V_CC capacitor must be sized such that the capacitor and V_CC self-bias maintains a V_CC voltage greater than 6.2 V during the initial start-up. During a fault mode when the converter auxiliary winding is inactive, external current draw on the V_CC line must be limited so the power dissipated in the start-up regulator does not exceed the maximum power dissipation of the controller.

An external start-up regulator or other bias rail can be used instead of the internal start-up regulator by connecting the V_CC and the V_IN pins together and feeding the external bias voltage into the two pins.

7.3.2 Line Undervoltage Detector

The LM5025 contains a line undervoltage lock out (UVLO) circuit. An external set-point voltage divider from Vin to GND, sets the operational range of the converter. The divider must be designed such that the voltage at the UVLO pin is greater than 2.5 V when Vin is in the desired operating range. If the undervoltage threshold is not met, all functions of the controller are disabled and the controller remains in a low-power standby state. UVLO hysteresis is accomplished with an internal 20-µA current source that is switched on or off into the impedance of the set-point divider. When the UVLO threshold is exceeded, the current source is activated to instantly raise the voltage at the UVLO pin. When the UVLO pin voltage falls below the 2.5-V threshold, the current source is turned off, causing the voltage at the UVLO pin to fall. The UVLO pin can also be used to implement a remote enable and disable function. Pulling the UVLO pin below the 2.5-V threshold disables the converter.

7.3.3 PWM Outputs

The relative phase of the main (OUT_A) and active clamp outputs (OUT_B) can be configured for the specific application. For active clamp configurations using a ground referenced P-channel clamp switch, the two outputs must be in phase with the active clamp output overlapping the main output. For active clamp configurations using a high side N-channel switch, the active clamp output must be out of phase with main output and there must be a dead time between the two gate drive pulses. A distinguishing feature of the LM5025 is the ability to accurately configure either dead time (both off) or overlap time (both on) of the gate driver outputs. The overlap and deadtime magnitude is controlled by the resistor value connected to the TIME pin of the controller. The opposite end of the resistor can be connected to either REF for deadtime control or GND for overlap control. The internal configuration detector senses the connection and configures the phase relationship of the main and active clamp outputs.

7.3.4 Compound Gate Drivers

The LM5025 contains two unique compound gate drivers, which parallel both MOS and bipolar devices to provide high-drive current throughout the entire switching event. The bipolar device provides most of the drive current capability and provides a relatively constant sink current that is ideal for driving large power MOSFETs. As the switching event nears conclusion and the bipolar device saturates, the internal MOS device continues to provide a low-impedance to compete the switching event.

During turnoff at the Miller plateau region, typically around 2 V to 3 V, is where gate driver current capability is needed most. The resistive characteristics of all MOS gate drivers are adequate for turnon, because the supply to output voltage differential is fairly large at the Miller region. During turnoff however, the voltage differential is small and the current source characteristic of the bipolar gate driver is beneficial to provide fast drive capability.

Figure 10. Compound Gate Drivers

7.3.5 PWM Comparator

The PWM comparator compares the ramp signal (RAMP) to the loop error signal (COMP). This comparator is optimized for speed to achieve minimum controllable duty cycles. The internal 5-kΩ pullup resistor, connected between the internal 5-V reference and COMP can be used as the pullup for an optocoupler. The comparator polarity is such that 0 V on the COMP pin produces a zero-duty cycle on both gate driver outputs.

7.3.6 Volt Second Clamp

The volt × second clamp comparator compares the ramp signal (RAMP) to a fixed 2.5-V reference. By proper selection of RFF and CFF, the maximum ON time of the main switch can be set to the desired duration. The ON time set by volt × second clamp varies inversely with the line voltage because the RAMP capacitor is charged by a resistor connected to Vin while the threshold of the clamp is a fixed voltage (2.5 V).

The C_FF ramp capacitor is discharged at the conclusion of every cycle by an internal discharge switch controlled by either the internal clock or by the V × S Clamp comparator, whichever event occurs first.

7.3.7 Current Limit

The LM5025 contains two modes of overcurrent protection. If the sense voltage at the CS1 input exceeds 0.25 V the present power cycle is terminated (cycle-by-cycle current limit). If the sense voltage at the CS2 input exceeds 0.25 V, the controller terminates the present cycle, discharge the soft-start capacitor and reduce the soft-start current source to 1 µA. The soft-start (SS) capacitor is released after being fully discharged and slowly charges with a 1-µA current source. When the voltage at the SS pin reaches approximately 1 V, the PWM comparator produces the first output pulse at OUT_A. After the first pulse occurs, the soft-start current source reverts to the normal 20-µA level. Fully discharging and then slowly charging the SS capacitor protects a continuously overloaded converter with a low-duty cycle hiccup mode.

These two modes of overcurrent protection allows the user great flexibility to configure the system behavior in overload conditions. If it is desired for the system to act as a current source during an overload, then the CS1 cycle-by-cycle current limiting must be used. In this case the current sense signal must be applied to the CS1 input and the CS2 input must be grounded. If during an overload condition it is desired for the system to briefly shutdown, followed by soft-start retry, then the CS2 hiccup current limiting mode must be used. In this case the current sense signal must be applied to the CS2 input and the CS1 input must be grounded. This shutdown and soft-start retry repeats indefinitely while the overload condition remains. The hiccup mode greatly reduces the thermal stresses to the system during heavy overloads. The cycle-by-cycle mode has higher system thermal dissipations during heavy overloads, but provides the advantage of continuous operation for short duration overload conditions.

In some systems it is possible use both modes concurrently, whereby slight overload conditions activate the CS1 cycle-by cycle mode, while more severe overloading activates the CS2 hiccup mode. Operating both modes concurrently requires that the slope of the inductor current be sufficient to reach the CS2 threshold before the CS1 function turns off the main output switch. This requires a high dv/dt at the current sense pin. The signal must be fast enough to reach the second-level threshold before the first threshold detector (CS1) turns off the gate driver. Excessive filtering on the CS pin, an extremely low-value current sense resistor or an inductor that does not saturate with excessive loading may prevent the second-level threshold from ever being reached.

TI recommends a small RC filter, located near the controller, for each of the CS pins. Each CS input has an internal FET that discharges the current sense filter capacitor at the conclusion of every cycle, to improve dynamic performance. This same FET remains on an additional 50 ns at the start of each main switch cycle to attenuate the leading edge spike in the current sense signal.

The LM5025 CS comparators are very fast and may respond to short duration noise pulses. Layout considerations are critical for the current sense filter and sense resistor. The capacitor associated with the CS filter must be placed very close to the device and connected directly to the pins of the IC (CS and GND). If a current sense transformer is used, both leads of the transformer secondary must be routed to the filter network , which must be located close to the IC. If a sense resistor in the source of the main switch MOSFET is used for current sensing, a low-inductance type of resistor is required. When designing with a current sense resistor, all of the noise sensitive low-power ground connections must be connected together near the IC GND and a single connection must be made to the power ground (sense resistor ground point).

Figure 11. Current Limit

7.3.8 Oscillator and Sync Capability

The LM5025 oscillator is set by a single external resistor connected between the RT pin and GND.

The RT resistor must be located very close to the device and connected directly to the pins of the IC (RT and GND).

A unique feature of LM5025 is the ability to synchronize the oscillator to an external clock with a frequency that is either higher or lower than the frequency of the internal oscillator. The lower frequency sync frequency range is 80% of the free running internal oscillator frequency. There is no constraint on the maximum SYNC frequency. A minimum pulse width of 100 ns is required for the synchronization clock . If the synchronization feature is not required, the SYNC pin must be connected to GND to prevent any abnormal interference. The internal oscillator can be completely disabled by connecting the RT pin to REF. Once disabled, the sync signal acts directly as the master clock for the controller. Both the frequency and the maximum duty cycle of the PWM controller can be controlled by the SYNC signal (within the limitations of the volt × second clamp). The maximum duty cycle (D) is (1D) of the SYNC signal.

7.3.9 Feed-Forward Ramp

An external resistor (R_FF) and capacitor (C_FF) connected to V_IN and GND are required to create the PWM ramp signal. The slope of the signal at the RAMP pin varies in proportion to the input line voltage. This varying slope provides line feedforward information necessary to improve line transient response with voltage mode control. The RAMP signal is compared to the error signal at the COMP pin by the pulse width modulator comparator to control the duty cycle of the main switch output. The volt second clamp comparator also monitors the RAMP pin and if the ramp amplitude exceeds 2.5 V the present cycle is terminated. The ramp signal is reset to GND at the end of each cycle by either the internal clock or the volt second comparator, whichever occurs first.

7.3.10 Soft-Start

The soft-start feature allows the power converter to gradually reach the initial steady state operating point, thus reducing start-up stresses and surges. At power on, a 20-µA current is sourced out of the soft-start pin (SS) into an external capacitor. The capacitor voltage ramps up slowly and limits the COMP pin voltage and therefore the PWM duty cycle. In the event of a fault as determined by V_CC undervoltage, line undervoltage (UVLO), or second-level current limit, the output gate drivers are disabled and the soft-start capacitor is fully discharged. When the fault condition is no longer present a soft-start sequence is initiated. Following a second-level current limit detection (CS2), the soft-start current source is reduced to 1 µA until the first output pulse is generated by the PWM comparator. The current source returns to the nominal 20-µA level after the first output pulse (approximately 1 V at the SS pin).

7.3.11 Thermal Protection

Internal thermal shutdown circuitry is provided to protect the integrated circuit in the event the maximum junction temperature is exceeded. When activated, typically at 165°C, the controller is forced into a low-power standby state with the output drivers and the bias regulator disabled. The device restarts after the thermal hysteresis (typically 25°C). During a restart after thermal shutdown, the soft-start capacitor is fully discharged and then charged in the low-current mode (1 µA) similar to a second-level current limit event. The thermal protection feature is provided to prevent catastrophic failures from accidental device overheating.