SNVSB14C April 2018 – October 2021 LM5036
PRODUCTION DATA
Figure 7-8 shows a simplified block diagram of the soft-start function.
The auxiliary supply has two reference output voltage levels of VAUX-OFF (1.4 -V typical, off state) and VAUX-ON (1-V typical, on state) which facilitates easy voltage level shift detection on the secondary side. The auxiliary supply starts to operate as soon as VIN > VAUX_UVLO (15-V typical) and VCC and REF are above the respective UV thresholds. When the soft-start capacitor is below VSSSecEn (2.06-V typical), the auxiliary supply will produce the off-state voltage on the primary (VAUX1-OFF) and secondary side (VAUX2-OFF), as shown in Figure 7-9.
The off-state auxiliary output voltage level present on the secondary side VAUX2-OFF is above the threshold VTHSec, which activates a reset circuit that discharges the output voltage reference VREFSec. This ensures that the opto-coupler is producing a 0% duty-cycle command. When UVLO exceeds VUVLO (1.25-V typical) and VCC and REF are above the respective UV thresholds, the soft-start capacitor starts to charge. The auxiliary supply will produce the on-state voltage level when the soft-start capacitor reaches VSSSecEn.
The secondary side reset circuit will now be disabled because VAUX2-ON < VTHSec, and the output voltage reference is released. The reference capacitor soft-starts the output voltage under full regulation. By modulation of the auxiliary output voltage, the communication between the primary and secondary side is established without the need of any additional opto-coupler.
Due to the introduced programmable soft-start delay (before SS capacitor reaches VSSSecEn), the duty cycle is controlled by the feedback control loop at all times without being interfered by the SS capacitor voltage (because VCOMP < VSS). When the reference voltage exceeds the pre-bias voltage at the output, the ICOMP starts to fall as the secondary side error amplifier demands increased power. As ICOMP falls the internal VCOMP voltage will rise and when it exceeds VSS-OS, which corresponds to zero duty cycle, the duty cycle of the primary FETs starts to increase. Once the ICOMP current falls below ICOSsrEn the device starts to charge SSSR capacitor with current ISSSR (20-µA typical).