SNVSB14 Data sheet

SNVSB14C April 2018 – October 2021 LM5036

PRODUCTION DATA

Package Options

Mechanical Data (Package|Pins)

RJB|28
- MPQF475

Thermal pad, mechanical data (Package|Pins)

Orderable Information

6.5 Electrical Characteristics

MIN and MAX limits apply the junction temperature range of –40°C ≤ T_J ≤ 125°C. Unless otherwise specified, the following conditions apply: V_IN = 48 V, R_T = 25 kΩ, RD₁ = RD₂ = 20 kΩ, R_ON = 100 kΩ. No load on LSG, HSG, SR1, SR2, UVLO = 2.5 V, ON_OFF = 0 V.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
START-UP REGULATOR
V_CC	V_CC voltage	I_CC = 10 mA	7.5	7.8	8.1	V
I_{CC (Lim)}	Vcc current limit	V_CC = 6 V, V_IN = 20 V	69	81	94	mA
I_CC(ext)	Vcc supply current	Supply current into Vcc from an externally applied source. V_CC = 9 V, FB_AUX = 0 V	6.6	9	11	mA
V_CC(reg)	Vcc load regulation	I_CC from 0 to 50 mA	31	49	73	mV
V_CC(UV)	Vcc undervoltage threshold	Positive going Vcc	7.4	7.7	8.0	V
		Negative going Vcc	6.1	6.3	6.7	V
	V_IN shutdown current	V_IN = 20 V, V_UVLO = 0 V, R_ON = 100 kΩ	276	580	670	µA
		V_IN = 100 V, V_UVLO = 0 V, R_ON = 100 kΩ	299	600	717	µA
	V_IN start-up regulator leakage	V_CC = 9 V, applied externally, FB_AUX > 2 V, SS = 0 V, R_ON = 100 kΩ	180	234	304	µA
VOLTAGE REFERENCE REGULATOR (REF PIN)
V_REF	REF voltage	I_REF = 0 mA	4.85	5	5.15	V
V_REF(REG)	REF load regulation	I_REF = 0 to 25 mA	24	37	57	mV
I_REF(LIM)	REF current limit	V_REF = 4.5 V, V_IN = 20 V	28	39	47	mA
V_REF(UV)	REF undervoltage threshold	Positive going V_REF	4.3	4.5	4.7	V
	Hysteresis		0.16	0.26	0.37	V
UNDERVOLTAGE LOCK OUT AND SHUTDOWN (UVLO PIN)
V_UVLO	UVLO threshold		1.205	1.25	1.305	V
I_UVLO	UVLO Hysteresis current		15	20	24	µA
V_SD	Internal startup regulator enable threshold	SS = 0 V, FB_AUX = 2.5 V	0.34	0.38	0.41	V
	Hysteresis		90	135	175	mV
OVER-VOLTAGE/LATCH (ON_OFF PIN)
V_{ON_OFF}	ON_OFF threshold		1.18	1.25	1.32	V
I_OVL	ON_OFF hysteresis current		40	50	60	µA
SOFT-START (SS PIN, SSSR PIN)
I_SS	SS charge current	SS = 0 V	17	20	24	µA
V_SSSecEn	SS threshold to enable SSSR charge current	I_COMP < 800 µA	1.93	2.06	2.2	V
	SS output low voltage	Sinking 100 µA	30	48	57	mV
	SS threshold to disable switching		865	1000	1198	mV
I_SSSR	SSSR charge current	SS > 2 V, I_COMP < 800 µA	17	20	24	µA
	SSSR output low voltage	Sinking 100 µA	30	38.7	49	mV
V_SSREn	SSSR threshold to enable SR freewheeling pulse		0.65	1.17	1.67	V
CURRENT SENSE (CS_POS, CS_NEG, and CS_SET PIN)
V_LIM	Current limit setting voltage		0.72	0.75	0.77	V
	Ratio of internal negative to positive current limit threshold		0.3	0.58	0.9
t_CSLSG	CS to gate driver output delay		60	85	122	ns
t_CSBLK	CS leading-edge blanking		33	53	76	ns
K_CBC1⁽¹⁾	V_LIM x (K_2a X K_10b - K_10a)	At CBC trip threshold	7.28	7.51	7.81	V
V_CSOffset⁽¹⁾	V_{CS_POS} - V_{CS_NEG}	At CBC trip threshold	-0.63	-0.02	0.32	mV
I_BiasOffset⁽¹⁾	I_BiasPOS - I_BiasNEG	At CBC trip threshold	-0.67	0.02	0.29	µA
I_SLOPE	Peak value of current source for slope compensation			36		µA
REVERSE CURRENT PROTECTION
N	Number of switching periods to reset negative over-current event counter			4
SR_CTR_TH	SSSR threshold to reset SSSR cap clamp event counter		4.8	4.94	5.1	V
HICCUP MODE (RES PIN)
R_RES	RES pulldown resistance	Termination of hiccup timer	24	36	55	Ω
V_RESTh1	RES hiccup threshold		0.90	1	1.04	V
V_RESTh3	RES upper counter threshold		3.91	4	4.07	V
V_RESTh2	RES lower counter threshold		1.95	2	2.04	V
I_RES-SRC1	Charge current source1	V_RES < 1 V, CBC active	12	15	18	µA
I_RES-SRC2	Charge current source2	1 V < V_RES< 4 V	25	30	36	µA
I_RES-DIS1	Discharge current source1	CBC not active	3.2	5	5.5	µA
I_RES-DIS2	Discharge current source2	2 V < V_RES < 4 V	2.5	5	7.5	µA
HICCUP MODE BLANKING
V_{HC_BLK_TH}	SSSR threshold to disable the hiccup blanking		5.26	5.5	5.66	V
VOLTAGE FEED-FORWARD (RAMP PIN)
	RAMP sink impednace (clocked)		3.9	6.0	9.1	Ω
OSCILLATOR (RT PIN)
f_SW1	Frequency (half oscillator frequency)	R_T = 25 kΩ	185	200	215	kHz
f_SW2	Frequency (half oscillator frequency)	R_T = 10 kΩ	420	480	540	kHz
V_RTReg	DC level		1.85	2	2.06	V
V_RTSync	RT sync threshold		2.8	3	3.3	V
SYNCHRONOUS RECTIFIER TIMING CONTROL (RD1 and RD2 PINS)
t₁	SR trailing edge delay SR turn-off to primary switch turn-on	RD₁ = 20 kΩ	94	123	157	ns
		RD₁ = 100 kΩ	213	278	350	ns
t₂	SR leading edge delay primary switch turn-off to SR turn-on	RD₂ = 20 kΩ	60	79	102	ns
		RD₂ = 100 kΩ	188	250	315	ns
t_clk	Pulse width of the clock		47	65	87	ns
COMP PIN
I_PWM-OS	COMP current to RAMP offset	RAMP = 0 V	596	800	1063	µA
V_SS-OS	SS to RAMP offset	RAMP = 0 V	0.86	1	1.15	V
	COMP current to RAMP gain	delta RAMP/delta I_COMP	1895	2400	2936	Ω
	SS to RAMP gain	delta SS/delta RAMP	0.574	0.646	0.74
I_COSsrEn	COMP current for SSSR charge curent enable	SS > 2 V	600	750	900	µA
	COMP to gate driver output delay		100	120	150	ns
	Minimum duty cycle	I_COMP = 1 mA			0	%
BOOST (BST PIN)
V_BST(UV)	BST under-voltage threshold	V_BST - V_SW rising	3.2	4.137	5.6	V
	Hysteresis		0.37	0.481	0.65	V
LSG, HSG GATE DRIVERS
V_{OL_PRI}	Low-state output voltage	I_HSG/LSG = 100 mA	0.1	0.3	0.41	V
V_{OH_PRI}	High-state output voltage	I_HSG/LSG = 100 mA, V_{OHL_PRI} = V_CC - V_LSG, V_{OHH_PRI} = V_BST - V_HSG	0	0.38	1	V
	Rise Time	C-load =1000 pF	2	8	12	ns
	Fall Time	C-load =1000 pF	2	10	14	ns
I_{SO_PRI}	Peak Source Current	V_HSG/LSG = 0V		1		A
I_{SI_PRI}	Peak Sink Current	V_HSG/LSG = VCC		2		A
SR1, SR2 GATE DRIVERS
V_{OL_SR}	Low-state output voltage	I_SR1/SR2 = 10 mA			0.12	V
V_{OH_SR}	High-state output voltage	I_SR1/SR2 = 10 mA, V_{OH_SR} = V_REF - V_SR			0.313	V
	Rise Time	C-load = 1000 pF	25	45	65	ns
	Fall Time	C-load = 1000 pF	4	10	16	ns
I_{SO_SR}	Peak Source Current	V_SR = 0 V	0.05	0.09	0.14	A
I_{SI_SR}	Peak Sink Current	V_SR = V_REF	0.1	0.2	0.4	A
HALF BRIDGE THERMAL SHUTDOWN
T_SD	Thermal Shutdown Temp			150		°C
	Thermal Shutdown Hysteresis			25		°C
AUX SUPPLY SWITCH CHARACTERISTICS
	Buck Switch R_DS(ON)	I_TEST= 60 mA	3.0	5.2	7.5	Ω
	Synchronous Switch R_DS(ON)	I_TEST= 60 mA	1.2	2.8	4.5	Ω
AUX SUPPLY UNDERVOLTAGE LOCKOUT
V_{BST_AUX(UV)}	BST_AUX undervoltage threshold	V_{BST_AUX} - V_{SW_AUX} rising	3.5	5.0	6.5	V
V_{AUX_UVLO}	AUX supply UVLO input voltage rising threshold		12.2	15	16.0	V
	AUX supply UVLO input voltage falling threshold		7.9	11.2	12.7	V
AUX SUPPLY REGULATION
V_AUX-OFF	OFF-State AUX Voltage Regulation Level		1.26	1.4	1.53	V
V_AUX-ON	ON-State AUX Voltage Regulation Level		0.95	1	1.04	V
AUX SUPPLY CURRENT LIMIT
I_AUX(LIM)	AUX Supply Current Limit Threshold		150	200	250	mA
t_CSBLKA	Current limit comparator blanking period measured from start of t_ON period ⁽¹⁾			50		ns
t_AUX(LIM)	Delay from Comparator Threshold to upper MOSFET turn-OFF ⁽¹⁾			116		ns
τ_AuxSns	Aux Current Limit Parasitic Filter time constant ⁽¹⁾			41		ns
AUX SUPPLY THERMAL SHUTDOWN
T_{SD_AUX}	AUX Supply Thermal Shutdown Temp			160		°C
	AUX Supply Thermal Shutdown Hysteresis			28		°C

(1) Specified by design. Not production tested.