SNVS703H February   2011  – November 2014 LM5046

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Handling Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  High-Voltage Start-Up Regulator
      2. 7.3.2  Line Undervoltage Detector
      3. 7.3.3  Overvoltage Protection
      4. 7.3.4  Reference
      5. 7.3.5  Oscillator, Sync Input
      6. 7.3.6  Cycle-by-Cycle Current Limit
      7. 7.3.7  Hiccup Mode
      8. 7.3.8  PWM Comparator
      9. 7.3.9  RAMP Pin
      10. 7.3.10 Slope Pin
      11. 7.3.11 Soft-Start
      12. 7.3.12 Gate Driver Outputs
      13. 7.3.13 Synchronous Rectifier Control Outputs (SR1 & SR2)
      14. 7.3.14 Soft-Start of the Synchronous Rectifiers
      15. 7.3.15 Pre-Bias Startup
      16. 7.3.16 Soft-Stop
      17. 7.3.17 Soft-Stop Off
      18. 7.3.18 Thermal Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Control Method Selection
      2. 7.4.2 Voltage Mode Control Using the LM5045
      3. 7.4.3 Current Mode Control Using the LM5045
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Phase-Shifted Full-Bridge Operation
          1. 8.2.2.1.1 Operating State 1 (Power Transfer/Active Mode)
          2. 8.2.2.1.2 Operating State 2 (Active to Passive Transition)
          3. 8.2.2.1.3 Operating State 3 (Freewheel/Passive Mode)
          4. 8.2.2.1.4 Operating State 4 (Passive to Active Transition)
        2. 8.2.2.2  Control Method Selection
        3. 8.2.2.3  Voltage Mode Control Using the LM5046
        4. 8.2.2.4  Current Mode Control Using the LM5046
        5. 8.2.2.5  VIN and VCC
        6. 8.2.2.6  For Applications With > 100 V Input
        7. 8.2.2.7  UVLO and OVP Voltage Divider Selection
        8. 8.2.2.8  Current Sense
        9. 8.2.2.9  Hiccup Mode Current Limit Restart
        10. 8.2.2.10 Augmenting the Gate Drive Strength
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Trademarks
    2. 11.2 Electrostatic Discharge Caution
    3. 11.3 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

28-Pin
HTSSOP
Top View
TSSOP28 Timing Diag.gif
28-Pin
WQFN
Top View
WQFN28 Pkg.gif

Pin Functions

PIN I/O DESCRIPTION APPLICATION INFORMATION
NAME 38 PIN TSSOP
NO.		 28 PIN TSSOP
NO.		 WQFN
NO.
UVLO 1 1 25 I Line Undervoltage Lockout An external voltage divider from the power source sets the shutdown and standby comparator levels. When UVLO reaches the 0.4 V threshold the VCC and REF regulators are enabled. At the 1.25 V threshold, the SS pin is released and the controller enters the active mode. Hysteresis is set by an internal current sink that pulls 20 µA from the external resistor divider.
OVP/OTP 2 2 26 I Overvoltage Protection An external voltage divider from the input power supply sets the shutdown level during an over-voltage condition. Alternatively, an external NTC thermistor voltage divider can be used to set the shutdown temperature. The threshold is 1.25 V. Hysteresis is set by an internal current that sources 20 µA of current into the external resistor divider.
RAMP 4 3 27 I Input to PWM Comparator Modulation ramp for the PWM comparator. This ramp can be a signal representative of the primary current (current mode) or proportional to the input voltage (feed-forward voltage mode). This pin is reset to GND at the end of every cycle.
CS 6 4 28 I Current Sense Input If CS exceeds 750 mV the PWM output pulse will be terminated, entering cycle-by-cycle current limit. An internal switch holds CS low for 40 nS after either output switches high to blank leading edge transients.
SLOPE 7 5 1 O Slope Compensation Current A ramping current source from 0 to 100 µA is provided for slope compensation in current mode control. This pin can be connected through an appropriate resistor to the CS pin to provide slope compensation. If slope compensation is not required, SLOPE must be tied to ground.
COMP 8 6 2 I Input to the Pulse Width Modulator An external opto-coupler connected to the COMP pin sources current into an internal NPN current mirror. The PWM duty cycle is at maximum with zero input current, while 1 mA reduces the duty cycle to zero. The current mirror improves the frequency response by reducing the AC voltage across the opto-coupler.
REF 9 7 3 O Output of a 5V reference Maximum output current is 15 mA. Locally decouple with a 0.1µF capacitor.
RT/SYNC 10 8 4 I Oscillator Frequency Control and Frequency Synchronization The resistance connected between RT and AGND sets the oscillator frequency. Synchronization is achieved by AC coupling a pulse to the RT/SYNC pin that raises the voltage at least 1.5 V above the 2 V nominal bias level.
AGND 11 9 5 I Analog Ground Connect directly to the Power Ground.
RD1 12 10 6 I Passive to Active Delay The resistance connected between RD1 and AGND sets the delay from the falling edge of HO1/SR1 or LO1/SR2 and the rising edge of LO1 or HO1 respectively.
RD2 13 11 7 I Active to Passive Delay The resistance connected between RD2 and AGND sets the delay from the falling edge of LO2 or HO2 and the rising edge of HO2 or LO2 respectively.
RES 16 12 8 I Restart Timer Whenever the CS pin exceeds the 750 mV cycle-by-cycle current limit threshold, 30 µA current is sourced into the RES capacitor for the remainder of the PWM cycle. If the RES capacitor voltage reaches 1.0 V, the SS capacitor is discharged to disable the HO1, HO2, LO1, LO2 and SR1, SR2 outputs. The SS pin is held low until the voltage on the RES capacitor has been ramped between 2 V and 4 V eight times by 10 µA charge and 5 µA discharge currents. After the delay sequence, the SS capacitor is released to initiate a normal start-up sequence.
SS 17 13 9 I Soft-Start Input An internal 20 µA current source charges the SS pin during start-up. The input to the PWM comparator gradually rises as the SS capacitor charges to steadily increase the PWM duty cycle. Pulling the SS pin to a voltage below 200 mV stops PWM pulses at HO1,2 and LO1,2 and turns off the synchronous rectifier FETs to a low state.
SSSR 18 14 10 I Secondary Side Soft-Start An external capacitor and an internal 20 µA current source set the soft-start ramp for the synchronous rectifiers. The SSSR capacitor charge-up is enabled after the first output pulse and SS > 2 V and Icomp < 800 µA
SSOFF 19 15 11 I Soft-Stop Disable When SS OFF pin is connected to the AGND, the LM5046 soft-stops in the event of a VIN UVLO and Hiccup mode current limit condition. If the SSOFF pin is connected to REF pin, the controller hard-stops on any fault condition. Refer to Table 1 for more details.
SR2 25 19 15 O Synchronous Rectifier Driver Control output for synchronous rectifier gate. Capable of peak sourcing 100 mA and sinking 400 mA.
VCC 27 21 17 I Output of Start-Up Regulator The output voltage of the start-up regulator is initially regulated to 9.5V. Once the secondary side soft-start (SSSR pin) reaches 1 V, the VCC output is reduced to 7.7 V. If an auxiliary winding raises the voltage on this pin above the regulation set-point, the internal start-up regulator will shutdown, thus reducing the IC power dissipation.
PGND 28 22 18 I Power Ground Connect directly to Analog Ground
LO1, LO2 29, 26 23, 20 19, 16 O Low Side Output Driver Alternating output of the PWM gate driver. Capable of 1.5A peak source and 2A peak sink current.
SR1 30 24 20 O Synchronous Rectifier Driver Control output for synchronous rectifier gate. Capable of peak sourcing 100 mA and sinking 400 mA.
BST1,2 33, 22 25, 18 21, 14 I Gate Drive Bootstrap Bootstrap capacitors connected between BST1, 2 and SW1, 2 provide bias supply for the high side HO1,2 gate drivers. External diodes are required between VCC and BST1,2 to charge the bootstrap capacitors when SW1,2 are low.
HO1,2 34, 21 26, 17 22, 13 O High Side Output Driver High side PWM outputs capable of driving the upper MOSFET of the bridge with 1.5A peak source and 2A peak sink current.
HS1,2 35, 20 27, 16 23, 12 O Switch Node Common connection of the high side FET source, low side FET drain and transformer primary winding.
VIN 38 28 24 I Input Power Source Input to the Start-up Regulator. Operating input range is 14 V to 100 V. For power sources outside of this range, the LM5046 can be biased directly at VCC by an external regulator.
NC 3, 5, 14, 15, 23, 24, 31, 32, 36, 37 - - - No Connect