SNVS628H October   2009  – December 2019 LM5060

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Typical Application Circuit
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-Up Sequence
      2. 7.4.2 Status Conditions
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1  Gate Control
      2. 8.1.2  Fault Timer
      3. 8.1.3  VGS Considerations
      4. 8.1.4  VDS Fault Condition
      5. 8.1.5  Overcurrent Fault
      6. 8.1.6  Restart After Overcurrent Fault Event
      7. 8.1.7  Enable
      8. 8.1.8  UVLO
      9. 8.1.9  OVP
      10. 8.1.10 Restart After OVP Event
      11. 8.1.11 nPGD Pin
    2. 8.2 Typical Applications
      1. 8.2.1 Example Number 1: LM5060EVAL Design
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 VDS Fault Detection and Selecting Sense Pin Resistor RS
          2. 8.2.1.2.2 Turn-On Time
          3. 8.2.1.2.3 Fault Detection Delay Time
          4. 8.2.1.2.4 MOSFET Selection
          5. 8.2.1.2.5 Input and Output Capacitors
          6. 8.2.1.2.6 UVLO, OVP
          7. 8.2.1.2.7 POWER GOOD Indicator
          8. 8.2.1.2.8 Input Bypass Capacitor
          9. 8.2.1.2.9 Large Load Capacitance
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Example Number 2: Reverse Polarity Protection With Diodes
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Application Curve
      3. 8.2.3 Example Number 3: Reverse Polarity Protection With Resistor
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Detailed Design Procedure
          1. 8.2.3.2.1 Reverse Polarity Protection With a Resistor
          2. 8.2.3.2.2 Fault Detection With RS and RO
        3. 8.2.3.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

Unless otherwise stated the following conditions apply: VIN = 14 V, EN = 2.00 V, UVLO = 2.00 V, OVP = 1.50 V, and TJ = 25°C. Limits in standard type are for TJ = 25°C except where noted. Minimum and Maximum limits are ensured through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN PIN
IIN-EN Input current, enabled mode TJ = 25°C 1.4 mA
TJ = –40°C to 125°C 1.7
IIN-DIS Input current, disabled mode EN = 0.50 V TJ = 25°C 9 µA
TJ = –40°C to 125°C 15
IIN-STB Input current, standby mode UVLO = 0.00 V TJ = 25°C 0.56 mA
TJ = –40°C to 125°C 0.80
POREN Power on reset threshold at VIN VIN rising TJ = 25°C 5.1 V
TJ = –40°C to 125°C 5.46
POREN-HYS POREN hysteresis VIN falling 500 mV
OUT PIN
IOUT-EN OUT pin bias current, enabled OUT = VIN, normal operation TJ = 25°C 8 µA
TJ = –40°C to 125°C 5.0 11.0
IOUT-DIS OUT pin leakage current, disabled(1) Disabled, OUT = 0 V, SENSE = VIN 0 μA
SENSE PIN
ISENSE Threshold programming current SENSE pin bias current TJ = 25°C 16 µA
TJ = –40°C to 125°C 13.6 18.0
VOFFSET VDS comparator offset voltage SENSE - OUT voltage for
fault detection		 TJ = 25°C 0 mV
TJ = –40°C to 125°C –7.0 7.0
IRATIO ISENSE and IOUT-EN current ratio ISENSE / IOUT-EN TJ = 25°C 2.0
TJ = –40°C to 125°C 1.70 2.30
OVP INPUT
OVPTH OVP threshold OVP pin threshold voltage rising TJ = 25°C 2.0 V
TJ = –40°C to 125°C 1.88 2.12
OVPHYS OVP hysteresis 240 mV
OVPDEL OVP delay time Delay from OVP pin > OVPTH to GATE low 9.6 µs
OVPBIAS OVP pin bias current OVP = 1.9 V TJ = 25°C 0 µA
TJ = –40°C to 125°C 0.50
UVLO INPUT
UVLOTH UVLO threshold UVLO pin threshold voltage rising TJ = 25°C 1.6 V
TJ = –40°C to 125°C 1.45 1.75
UVLOHYS UVLO hysteresis TJ = 25°C 180 mV
TJ = –40°C to 125°C 120 230
UVLOBIAS UVLO pin pull-down current TJ = 25°C 5.5 µA
TJ = –40°C to 125°C 3.8 7.2
EN INPUT
ENTHH High-level input voltage TJ = –40°C to 125°C 2.00 V
ENTHL Low-level input voltage TJ = –40°C to 125°C 0.80 V
ENHYS EN threshold hysteresis 200 mV
ENBIAS EN pin pull-down current TJ = 25°C 6 µA
TJ = –40°C to 125°C 8.0
GATE CONTROL (GATE PIN)
IGATE Gate charge (sourcing) current, on state On-state TJ = 25°C 24 µA
TJ = –40°C to 125°C 17 31
IGATE-OFF Gate discharge (sinking) current, off state UVLO = 0.00 V 2.2 mA
IGATE-FLT Gate discharge (sinking) current, fault state OUT < SENSE 80 mA
VGATE Gate output voltage in normal operation GATE - VIN voltage
GATE pin open		 TJ = 25°C 12 V
TJ = –40°C to 125°C 10 14
VGATE-TH VGS status comparator threshold voltage GATE - OUT threshold voltage for TIMER voltage reset and
TIMER current change		 TJ = 25°C 5 V
TJ = –40°C to 125°C 3.50 6.50
VGATE-CLAMP Zener clamp between GATE pin and OUT pin IGATE-CLAMP = 0.1 mA 16.8 V
TIMER (TIMER PIN)
VTMRH Timer fault threshold TIMER pin voltage rising 2.0 V
VTMRL Timer re-enable threshold TIMER pin voltage falling 0.30 V
ITIMERH Timer charge current for VDS fault TIMER charge current
after start-up
VGS = 6.5 V		 TJ = 25°C 11 µA
TJ = –40°C to 125°C 8.5 13.0
ITIMERL Timer start-up charge current TIMER charge current
during start-up
VGS = 3.5 V		 TJ = 25°C 6 µA
TJ = –40°C to 125°C 4.0 7.0
ITIMERR Timer reset discharge current TIMER pin = 1.5 V TJ = 25°C 6 mA
TJ = –40°C to 125°C 4.4 8.2
tFAULT Fault to GATE low delay TIMER pin > 2.0 V
No load on GATE pin		 5 µs
POWER GOOD (nPGD PIN)
PGDVOL Output low voltage ISINK = 2 mA TJ = 25°C 80 mV
TJ = –40°C to 125°C 205
PGDIOH Off leakage current VnPGD = 10 V TJ = 25°C 0.02 µA
TJ = –40°C to 125°C 1.00
(1) The GATE pin voltage is typically 12 V above the VIN pin when the LM5060 is enabled. Therefore, the Absolute Maximum Rating for VIN (75 V) applies only when the LM5060 is disabled, or for a momentary surge to that voltage since the Absolute Maximum Rating for the GATE pin is also 75 V.