SNVS628H October   2009  – December 2019 LM5060

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Typical Application Circuit
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-Up Sequence
      2. 7.4.2 Status Conditions
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1  Gate Control
      2. 8.1.2  Fault Timer
      3. 8.1.3  VGS Considerations
      4. 8.1.4  VDS Fault Condition
      5. 8.1.5  Overcurrent Fault
      6. 8.1.6  Restart After Overcurrent Fault Event
      7. 8.1.7  Enable
      8. 8.1.8  UVLO
      9. 8.1.9  OVP
      10. 8.1.10 Restart After OVP Event
      11. 8.1.11 nPGD Pin
    2. 8.2 Typical Applications
      1. 8.2.1 Example Number 1: LM5060EVAL Design
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 VDS Fault Detection and Selecting Sense Pin Resistor RS
          2. 8.2.1.2.2 Turn-On Time
          3. 8.2.1.2.3 Fault Detection Delay Time
          4. 8.2.1.2.4 MOSFET Selection
          5. 8.2.1.2.5 Input and Output Capacitors
          6. 8.2.1.2.6 UVLO, OVP
          7. 8.2.1.2.7 POWER GOOD Indicator
          8. 8.2.1.2.8 Input Bypass Capacitor
          9. 8.2.1.2.9 Large Load Capacitance
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Example Number 2: Reverse Polarity Protection With Diodes
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Application Curve
      3. 8.2.3 Example Number 3: Reverse Polarity Protection With Resistor
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Detailed Design Procedure
          1. 8.2.3.2.1 Reverse Polarity Protection With a Resistor
          2. 8.2.3.2.2 Fault Detection With RS and RO
        3. 8.2.3.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.1.2 Fault Timer

An external capacitor connected from the TIMER pin to the GND pin sets the fault detection delay time. If the voltage on the TIMER capacitor reaches the VTMRH threshold (2 V typical) a fault condition is indicated. The LM5060 will latch off the MOSFET by discharging the GATE pin at a 80 mA (typical) rate, and will remain latched off until either the EN pin, the UVLO pin, or the VIN pin is toggled low and then high.

There are three relevant components to the TIMER pin’s function:

  1. A constant 6-µA (typical) current source driving the TIMER pin. This current source is active when EN, UVLO, and VIN are all high.
  2. A second current source (5 µA typical) is activated, for a total charge current of 11 µA (typical), only when the VGS sequence has completed successfully.
  3. A pull-down current sink for the TIMER pin which resets the timer by discharging the timer capacitor. If EN, UVLO or VIN is low, or when OVP is high, the timer capacitor is discharged.
    1. When the VDS Fault Comparator detects a fault, (SENSE pin voltage higher than OUT pin voltage) the timer capacitor pull down is disabled and the timer capacitor is allowed to charge at the 11-µA (typical) rate.

During Start-Up, the timer behaves as follows:

After applying sufficient system voltage and enabling the LM5060 by pulling the EN and UVLO pins high, the timer capacitor will be charged with a 6-µA (typical) current source. The timer capacitor is discharged when the voltage difference between the GATE pin and the OUT pin (i.e. VGS of the external N-Channel MOSFET) reaches the VGATE-TH threshold (typically 5 V). After discharging, the timer capacitor is charged with 11 µA until either the VTMRH threshold (typically 2 V) is reached, or the sensed VDS voltage falls below the threshold of the VDS Fault Comparator, indicating the output voltage has reached the desired steady state level. The timer capacitor voltage waveforms are illustrated in Figure 21, Figure 22, and Figure 23.

A timer capacitor is always necessary to allow some finite amount of time for the gate to charge and the output voltage to rise during startup. If an adequate timer capacitor value is not used, then the 6 µA of charge current would cause the TIMER pin voltage to reach the VTMRH fault threshold (typically 2 V) prematurely and the LM5060 will latch off since a fault condition would have been indicated.

Although not recommended, the timer function can be disabled by connecting the TIMER pin directly to GND. With this condition the TIMER pin voltage will never reach the VTMRH fault threshold (2 V typical). The end result is that the fault latch-off protection is completely disabled, while the nPGD pin will continue to reflect the VDS Fault Comparator output.