7.3.1 Regulation Control Circuit

The LM5085 buck DC-DC controller employs a control scheme based on a comparator and a one-shot on-timer, with the output voltage feedback compared to an internal reference voltage (1.25V). When the FB pin voltage falls below the feedback reference, Q1 is switched on for a time period determined by the input voltage and a programming resistor (R_T). Following the on-time Q1 remains off until the FB voltage falls below the reference. Q1 is then switched on for another on-time period. The output voltage is set by the feedback resistors (R_FB1, R_FB2 in the Block Diagram). The regulated output voltage is calculated as follows:

The feedback voltage supplied to the FB pin is applied to a comparator rather than a linear amplifier. For proper operation sufficient ripple amplitude is necessary at the FB pin to switch the comparator at regular intervals with minimum delay and noise susceptibility. This ripple is normally obtained from the output voltage ripple attenuated through the feedback resistors. The output voltage ripple is a result of the inductor’s ripple current passing through the output capacitor’s ESR, or through a resistor in series with the output capacitor. Multiple methods are available to ensure sufficient ripple is supplied to the FB pin, and three different configurations are discussed in the Typical Application section.

When in regulation, the LM5085 operates in continuous conduction mode at medium to heavy load currents and discontinuous conduction mode at light load currents. In continuous conduction mode the inductor’s current is always greater than zero, and the operating frequency remains relatively constant with load and line variations. The minimum load current for continuous conduction mode is one-half the inductor’s ripple current amplitude. In discontinuous conduction mode, where the inductor’s current reaches zero during the off-time, the operating frequency is lower than in continuous conduction mode and varies with load current. Conversion efficiency is maintained at light loads since the switching losses are reduced with the reduction in load and frequency.

If the voltage at the FB pin exceeds 1.6V due to a transient overshoot or excessive ripple at V_OUT the internal over-voltage comparator immediately switches off Q1. The next on-time period starts when the voltage at FB falls below the feedback reference voltage.

7.3.2 On-Time Timer

The on-time of the PFET gate drive output (PGATE pin) is determined by the resistor (R_T) and the input voltage (V_IN), and is calculated from:

Equation 3.

where R_T is in kΩ.

The minimum on-time, which occurs at maximum V_IN, should not be set less than 150ns (see Current Limiting section). The buck regulator effective on-time, measured at the SW node (junction of Q1, L1, and D1) is typically longer than that calculated in Equation 3 due to the asymmetric delay of the PFET. The on-time difference caused by the PFET switching delay can be estimated as the difference of the turn-off and turn-on delays listed in the PFET data sheet. Measuring the difference between the on-time at the PGATE pin versus the SW node in the actual application circuit is also recommended.

In continuous conduction mode, the inverse relationship of t_ON with V_IN results in a nearly constant switching frequency as V_IN is varied. The operating frequency can be calculated from:

Equation 4.

where R_T is in kΩ, and t_D is equal to 50ns plus the PFET’s delay difference. To set a specific continuous conduction mode switching frequency (F_S), the R_T resistor is determined from the following:

Equation 5.

where R_T is in kΩ. A simplified version of Equation 5 at V_IN = 12V, and t_D = 100ns, is:

Equation 6.

For V_IN = 48V and t_D = 100ns, the simplified equation is:

Equation 7.

7.3.3 Shutdown

The LM5085 can be shutdown by grounding the RT pin (see Figure 22). In this mode the PFET is held off, and the VCC regulator is disabled. The internal operating current is reduced to the value shown in the graph “Shutdown current vs. VIN”. The shutdown threshold at the RT pin is ≊0.73V, with ≊50mV of hysteresis. Releasing the pin enables normal operation. The RT pin must not be forced high during normal operation.

Figure 22. Shutdown Implementation

7.3.4 Current Limiting

The LM5085 current limiting operates by sensing the voltage across either the R_DS(ON) of Q1, or a sense resistor, during the on-time and comparing it to the voltage across the resistor R_ADJ (see Figure 23). The current limit function is much more accurate and stable over temperature when a sense resistor is used. The R_DS(ON) of a MOSFET has a wide process variation and a large temperature coefficient.

If the voltage across R_DS(ON) of Q1, or the sense resistor, is greater than the voltage across R_ADJ, the current limit comparator switches to turn off Q1. Current sensing is disabled for a blanking time of ≊100ns at the beginning of the on-time to prevent false triggering of the current limit comparator due to leading edge current spikes. Because of the blanking time and the turn-on and turn-off delays created by the PFET, the on-time at the PGATE pin should not be set less than 150ns. An on-time shorter than that may prevent the current limit detection circuit from properly detecting an over-current condition. The duration of the subsequent forced off-time is a function of the input voltage and the voltage at the FB pin, as shown in the graph “Off-time vs. V_IN and V_FB”. The longer-than-normal forced off-time allows the inductor current to decrease to a low level before the next on-time. This cycle-by-cycle monitoring, followed by a forced off-time, provides effective protection from output load faults over a wide range of operating conditions.

The voltage across the R_ADJ resistor is set by an internal 40µA current sink at the ADJ pin. When using Q1’s R_DS(ON) for sensing, the current at which the current limit comparator switches is calculated from:

When using a sense resistor (R_SEN) the threshold of the current limit comparator is calculated from:

When using Equation 8 or Equation 9, the tolerances for the ADJ pin current sink and the offset of the current limit comparator should be included to ensure the resulting minimum current limit is not less than the required maximum switch current. Simultaneously increasing the values of R_ADJ and R_SEN decreases the effects of the current limit comparator offset, but at the expense of higher power dissipation. When using a sense resistor, the R_SEN resistor value should be chosen within the practical limitations of power dissipation and physical size. For example, for a 10A current limit, setting R_SEN = 0.005Ω results in a power dissipation as high as 0.5W. Current sense connections to the R_SEN resistor, or to Q1, must be Kelvin connections to ensure accuracy.

The C_ADJ capacitor filters noise from the ADJ pin, and helps prevent unintended switching of the current limit comparator due to input voltage transients. The recommended value for C_ADJ is 1000pF.

7.3.5 Current Limit Off-Time

When the current through Q1 exceeds the current limit threshold, the LM5085 forces an off-time longer than the normal off-time defined by Equation 1. See the graph “Off-Time vs. V_IN and V_FB”, or calculate the current limit off-time from the following equation:

Equation 10.

where V_IN is the input voltage, and V_FB is the voltage at the FB pin at the time current limit was detected. This feature is necessary to allow the inductor current to decrease sufficiently to offset the current increase which occurred during the on-time. During the on-time, the inductor current increases an amount equal to:

Equation 11.

During the off-time the inductor current decreases due to the reverse voltage applied across the inductor by the output voltage, the freewheeling diode’s forward voltage (V_FD), and the voltage drop due to the inductor’s series resistance (V_ESR). The current decrease is equal to:

Equation 12.

The on-time in Equation 11 is shorter than the normal on-time since the PFET is shut off when the current limit threshold is crossed. If the off-time is not long enough, such that the current decrease (Equation 12) is less than the current increase (Equation 11), the current levels are higher at the start of the next on-time. This results in a further decrease in on-time, since the current limit threshold is crossed sooner. A balance is reached when the current changes in Equation 11 and Equation 12 are equal. The worst case situation is that of a direct short circuit at the output terminals, where V_OUT = 0V, as that results in the largest current increase during the on-time, and the smallest decrease during the off-time. The sum of the diode’s forward voltage and the inductor’s ESR voltage must be sufficient to ensure current runaway does not occur. Using Equation 11 and Equation 12, this requirement can be stated as:

Equation 13.

For t_ON in Equation 13, use the minimum on-time at the SW node. To determine this time period add the “Minimum On-Time in Current Limit” specified in the Electrical Characteristics (t_ON-4) to the difference of the turn-off and turn-on delays of the PFET. For t_OFF use the value in the graph “Off-Time vs. V_IN and V_FB”, or use Equation 10, where V_FB is equal to zero volts. When using the minimum or maximum limits of those specifications to determine worst case situations, the tolerance of the minimum on-time (t_ON-4) and the current limit off-times (t_OFF(CL1) through t_OFF(CL4)) track each other over the process and temperature variations. A device which has an on-time at the high end of the range will have an off-time that is at the high end of its range.

Figure 23. Current Limit Sensing

7.3.6 VCC Regulator

The VCC regulator provides a regulated voltage between the VIN and the VCC pins to provide the bias and gate current for the PFET gate driver. The 0.47µF capacitor at the VCC pin must be a low ESR capacitor, preferably ceramic as it provides the high surge current for the PFET’s gate at each turn-on. The capacitor must be located as close as possible to the VIN and VCC pins to minimize inductance in the PC board traces.

Referring to Figure 4 “VCC vs. VIN”, the voltage across the VCC regulator (VIN – VCC) is equal to VIN until VIN reaches approximately 8.5V. At higher values of VIN, the voltage at the VCC pin is regulated at approximately 7.7V below VIN. If VIN drops below about 8V due to voltage transients, the VCC pin can be pulled down below GND. To prevent the negative VCC voltage from disturbing the internal circuit and causing abnormal operation, Figure 24 shows the required placement of this Schottky diode between the VCC pin and GND pin. The Schottky diode should be placed as close as possible to the VCC pin. The VCC regulator has a maximum current capability of at least 20mA. The regulator is disabled when the LM5085 is shutdown using the RT pin, or when the thermal shutdown is activated.

Figure 24. Schottky Diode at VCC Pin During VIN Negative Transients (VIN < 8 V)

7.3.7 PGATE Driver Output

The PGATE pin output swings between V_IN (Q1 off) and the VCC pin voltage (Q1 on). The rise and fall times depend on the PFET gate capacitance and the source and sink currents provided by the internal gate driver. See the Electrical Characteristics for the current capability of the driver.

7.3.8 P-Channel MOSFET Selection

The PFET must be rated for the maximum input voltage, with some margin above that to allow for transients and ringing which can occur on the supply line and the switching node. The gate-to-source voltage (V_GS) normally provided to the PFET is 7.7V for VIN greater than 8.5V. However, if the circuit is to be operated at lower values of VIN, the selected PFET must be able to fully turn-on with a V_GS voltage equal to VIN. The minimum input operating voltage for the LM5085 is 4.5V.

Similar to NFETs, the case or exposed thermal pad for a PFET is electrically connected to the drain terminal. When designing a PFET buck regulator the drain terminal is connected to the switching node. This situation requires a trade-off between thermal and EMI performance since increasing the PC board area of the switching node to aid the PFET power dissipation also increases radiated noise, possibly disrupting the circuit operation. Typically the switching node area is kept to a reasonable minimum and the PFET peak current is derated to stay within the recommended temperature rating of the PFET. The R_DS(ON) of the PFET determines a portion of the power dissipation in the PFET. However, PFETs with very low R_DS(ON) usually have large values of gate charge. A PFET with a higher gate charge has a corresponding slower switching speed, leading to higher switching losses and affecting the PFET power dissipation.

If the PFET R_DS(ON) is used for current limit detection, note that it typically has a positive temperature coefficient. At 100°C the R_DS(ON) may be as much as 50% higher than the value at 25°C which could result in incorrect current limiting if not accounted for when determining the value of the R_ADJ resistor. The PFET Total Gate Charge determines most of the power dissipation in the LM5085 due to the repetitive charge and discharge of the PFET’s gate capacitance by the gate driver (powered from the VCC regulator). The LM5085’s internal power dissipation can be calculated from the following:

where Q_G is the PFET's Total Gate Charge obtained from its datasheet, F_S is the switching frequency, and I_IN is the LM5085's operating current obtained from the graph "Input Operating Current vs. V_IN". Using the Thermal Resistance specifications in the Electrical Characteristics table, the approximate junction temperature can be determined. If the calculated junction temperature is near the maximum operating temperature of 125°C, either the switching frequency must be reduced, or a PFET with a smaller Total Gate Charge must be used.

7.3.9 Soft-Start

The internal soft-start feature of the LM5085 allows the regulator to gradually reach a steady state operating point at power up, thereby reducing startup stresses and current surges. Upon turn-on, when Vcc reaches its under-voltage lockout threshold, the internal soft-start circuit ramps the feedback reference voltage from 0V to 1.25V, causing V_OUT to ramp up in a proportional manner. The soft-start ramp time is typically 2.5ms.

In addition to controlling the initial power up cycle, the soft-start circuit also activates when the LM5085 is enabled by releasing the RT pin, and when the circuit is shutdown and restarted by the internal Thermal Shutdown circuit.

If the voltage at FB is below the regulation threshold value due to an over-current condition or a short circuit at V_OUT, the internal reference voltage provided by the soft-start circuit to the regulation comparator is reduced along with FB. When the over-current or short circuit condition is removed, V_OUT returns to the regulated value at a rate determined by the soft-start ramp. This feature helps prevent the output voltage from overshooting following an overload event.

7.3.10 Thermal Shutdown

The LM5085 should be operated such that the junction temperature does not exceed 125°C. If the junction temperature increases above that, an internal Thermal Shutdown circuit activates at 170°C (typical) to disable the VCC regulator and the gate driver, and discharge the soft-start capacitor. This feature helps prevent catastrophic failures from accidental device overheating. When the junction temperature falls below 150°C (typical hysteresis = 20°C), the gate driver is enabled, the soft-start circuit is released, and normal operation resumes.

7.4.1 Standby Mode with VIN <4.5 V

The LM5085 is intended to operate with input voltages above 4.5 V. The minimum operating input voltage is determined by the VCC undervoltage lockout threshold of 3.8 V (typ). If V_IN is too low to support a VCC voltage greater than the VCC UVLO threshold, the controller switches to the standby mode with the PFET buck switch in the off state.

7.4.2 RT Shutdown Mode

The LM5085 is in shutdown mode when the RT pin is pulled below 0.73 V (typ). In this mode, the PFET gate driver is held off and the VCC regulator is disabled.