Selection of the buck MOSFET is governed by the same trade-offs as the switching frequency. Losses in power MOSFETs can be broken down into conduction losses and switching losses. The conduction loss is given by Equation 23.

where

• D is the duty cycle.
• I_O is the maximum load current.

The factor 1.3 accounts for the increase in MOSFET on-resistance due to heating. Alternatively, for a more precise calculation, the factor of 1.3 can be ignored and the on-resistance of the MOSFET can be estimated using the R_DS(ON) vs Temperature curves in the MOSFET data sheet.

The switching loss occurs during the brief transition period as the MOSFET turns on and off. During the transition period both current and voltage are present in the MOSFET. The switching loss can be approximated as:

where

• t_Ris the rise time of the MOSFET.
• t_F is the fall time of the MOSFET.

The rise and fall times are usually mentioned in the MOSFET data sheet or can be empirically observed on the scope. There is another loss, which is associated with the buck MOSFET is the gate-charging loss. This loss differs from the above two losses in the sense that it is dissipated in the LM5088 and not in the MOSFET itself. Gate charging loss, P_GC, results from the drive current charging the gate capacitance of the power MOSFET and is approximated as:

For this example with the maximum input voltage of 55 V, the V_DS breakdown rating of the selected MOSFET must be greater than 55 V, plus any ringing across drain to source due to parasitics. In order to minimize switching time and gate drive losses, the selected MOSFET must also have low gate charge (Q_g). A good choice of MOSFET for this design example is the SI7148DP which has a total gate charge of 30 nC and rise and fall times of 10 ns and 12 ns, respectively.