SNOSAW2Q September   2006  – November 2015 LM5100A , LM5100B , LM5100C , LM5101A , LM5101B , LM5101C

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Start-up and UVLO
      2. 8.3.2 Level Shift
      3. 8.3.3 Bootstrap Diode
      4. 8.3.4 Output Stages
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Select Bootstrap and VDD capacitor
        2. 9.2.2.2 Select External Bootstrap Diode and Resistor
        3. 9.2.2.3 Select Gate driver Resistor
        4. 9.2.2.4 Estimate the Driver Power Losses
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Detailed Description

8.1 Overview

The LM5100A/B/C and LM5101A/B/C are designed to drive both the high-side and the low-side N-channel FETs in a synchronous buck or a half-bridge configuration. The outputs are independently controlled with CMOS input thresholds(LM5101A/B/C) or TTL input thresholds(LM5101A/B/C). The floating high-side driver is capable of working with supply voltages up to 100 V. An integrated high voltage diode is provided to charge high side gate drive bootstrap capacitor. A robust level shifter operates at high speed while consuming low power and providing clean level transitions from the control logic to the high side gate driver. Under-voltage lockout is provided on both the low side and the high side power rails.

8.2 Functional Block Diagram

LM5100A LM5100B LM5100C LM5101A LM5101B LM5101C fbd_snosaw2.gif

8.3 Feature Description

8.3.1 Start-up and UVLO

Both high and low-side drivers include under voltage lockout (UVLO) protection circuitry which monitors the supply voltage (VDD) and bootstrap capacitor voltage (VHB–HS) independently. The UVLO circuit inhibits each driver until sufficient supply voltage is available to turn on the external MOSFETs, and the built-in UVLO hysteresis prevents chattering during supply voltage transitions. When the supply voltage is applied to the VDD pin of the LM5100A/B/C and LM5101A/B/C, the outputs of the low-side and high-side are held low until VDD exceeds the UVLO threshold, typically about 6.6 V. Any UVLO condition on the bootstrap capacitor will disable only the high-side output (HO).

8.3.2 Level Shift

The level shift circuit is the interface from the high-side input to the high-side driver stage which is referenced to the switch node (HS). The level shift allows control of the HO output referenced to the HS pin and provides excellent delay matching with the low-side driver.

8.3.3 Bootstrap Diode

The bootstrap diode necessary to generate the high-side bias is included in the LM5100/1 family. The diode anode is connected to VDD and cathode connected to VHB. With the VHB capacitor connected to HB and the HS pins, the VHB capacitor charge is refreshed every switching cycle when HS transitions to ground. The boot diode provides fast recovery times, low diode resistance, and voltage rating margin to allow for efficient and reliable operation.

8.3.4 Output Stages

The output stages are the interface to the power MOSFETs in the power train. High slew rate, low resistance, and high peak current capability of both output drivers allow for efficient switching of the power MOSFETs. The low-side output stage is referenced from VDD to VSS and the high-side is referenced from VHB to VHS.

8.4 Device Functional Modes

The device operates in normal mode and UVLO mode. See Start-up and UVLO for more information on UVLO operation mode. In normal mode, the output stage is dependent on the states of the HI and LI pins.

Table 1. Input/Output Logic Table

HI LI HO(1) LO(2)
L L L L
L H L H
H L H L
H H H H
x(3) x L L
(1) HO is measured with respect to the HS.
(2) LO is measured with the respect to the VSS.
(3) x is floating condition