SNVS269D January   2004  – December 2014 LM5104

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Adaptive Shoot-Through Protection
      2. 7.3.2 Start-up and UVLO
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Power Dissipation Considerations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Trademarks
    2. 11.2 Electrostatic Discharge Caution
    3. 11.3 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

The LM5104 is one of the latest generation of high-voltage gate drivers which are designed to drive both the high-side and low-side N-channel MOSFETs in a half-bridge/full bridge configuration or in a synchronous buck circuit. The floating high-side driver can operate with supply voltages up to 100 V. This allows for N-channel MOSFET control in half-bridge, full-bridge, push-pull, two switch forward and active clamp topologies.

Table 1. Highlights

FEATURE BENEFIT
Adaptive Rising and Falling Edges with Programmable Additional Delay Allows optimization of gate drive timings to account for device differences between high-side and low-side positions.
Single Input Control Direct drive from lower cost PWM controllers
Internal Bootstrap Diode Reduces parts count and PCB real estate

8.2 Typical Application

20089009.gifFigure 15. LM5104 Driving MOSFETs Connected in Synchronous Buck Configuration

8.2.1 Design Requirements

PARAMETER VALUE
Gate Driver IC LM5104
Mosfet CSD18531Q5A
VDD 10 V
Qgmax 43 nC
Fsw 200 kHz
DMax 95%
IHBO 10 µA
VDH 1.1 V
VHBR 7.1 V
VHBH 0.4 V

8.2.2 Detailed Design Procedure

Equation 1. ΔVHB = VDD – VDH – VHBL

where

  • VDD = Supply voltage of the gate drive IC
  • VDH = Bootstrap diode forward voltage drop
  • Vgsmin = Minimum gate source threshold voltage
Equation 2. equation1_snvs268.gif
Equation 3. equation2_snvs268.gif

The quiescent current of the bootstrap circuit is 10 µA which is negligible compared to the Qgs of the MOSFET.

Equation 4. equation3_snvs268.gif
Equation 5. QTOTAL = 43.01 nC

In practice the value for the CBOOT capacitor should be greater than that calculated to allow for situations where the power stage may skip pulse due to load transients. In this circumstance the boot capacitor must maintain the HB pin voltage above the UVLO voltage for the HB circuit.

As a general rule the local VDD bypass capacitor should be 10 times greater than the value of CBOOT.

Equation 6. VHBL = VHBR – VHBH
Equation 7. VHBL = 6.7 V
Equation 8. ΔVHB = 10 V – 1.1 V – 6.7 V
Equation 9. ΔVHB = 2.2 V
Equation 10. equation4_snvs268.gif
Equation 11. CBOOT = 19.54 nF

The bootstrap and bias capacitors should be ceramic types with X7R dielectric. The voltage rating should be twice that of the maximum VDD to allow for loss of capacitance once the devices have a DC bias voltage across them and to ensure long-term reliability of the devices.

An additional delay turn-on delay can be programmed using an external resistor, RT. Figure 17 shows the relationship between the turnon delay time and the resistor value for RT.

8.2.3 Application Curves

20089005.gifFigure 16. Application Timing Waveforms
20089014.gifFigure 17. Turn On Delay vs RT Resistor Value