SNVS269D January   2004  – December 2014 LM5104

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Adaptive Shoot-Through Protection
      2. 7.3.2 Start-up and UVLO
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Power Dissipation Considerations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Trademarks
    2. 11.2 Electrostatic Discharge Caution
    3. 11.3 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

D Package
8-Pin SOIC
Top View
20089001.gif
DPR Package
10-Pin WSON
Top View
20089002.gif

Pin Functions

PIN NAME DESCRIPTION APPLICATION INFORMATION
SOIC WSON
1 1 VDD Positive gate drive supply Locally decouple to VSS using ESR/ESL capacitor, located as close to IC as possible.
2 2 HB High-side gate driver bootstrap rail Connect the positive terminal to bootstrap capacitor to the HB pin and connect negative terminal to HS. The Bootstrap capacitor should be placed as close to IC as possible
3 3 HO High-side gate driver output Connect to gate of high-side MOSFET with short low inductance path.
4 4 HS High-side MOSFET source connection Connect to bootstrap capacitor negative terminal and source of high-side MOSFET.
5 7 RT Deadtime programming pin Resistor from RT to ground programs the deadtime between high- and low-side transitions. The resistor should be located close to the IC to minimize noise coupling from adjacent traces.
6 8 IN Control input Logic 1 equals High-side ON and Low-side OFF. Logic 0 equals High-side OFF and Low-side ON.
7 9 VSS Ground return All signals are referenced to this ground.
8 10 LO Low-side gate driver output Connect to the gate of the low-side MOSFET with a short low inductance path.