SNVS725I June   2011  – October 2019 LM5113

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Application Diagram
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input and Output
      2. 7.3.2 Start-Up and UVLO
      3. 7.3.3 HS Negative Voltage and Bootstrap Supply Voltage Clamping
      4. 7.3.4 Level Shift
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 VDD Bypass Capacitor
        2. 8.2.2.2 Bootstrap Capacitor
        3. 8.2.2.3 Power Dissipation
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

3 Description

The LM5113 device is designed to drive both the high-side and the low-side enhancement mode Gallium Nitride (GaN) FETs in a synchronous buck or a half bridge configuration. The floating high-side driver is capable of driving a high-side enhancement mode GaN FET operating up to 100 V. The high-side bias voltage is generated using a bootstrap technique and is internally clamped at 5.2 V, which prevents the gate voltage from exceeding the maximum gate-source voltage rating of enhancement mode GaN FETs. The inputs of the LM5113 are TTL logic compatible, and can withstand input voltages up to 14 V regardless of the VDD voltage. The LM5113 has split gate outputs, providing flexibility to adjust the turnon and turnoff strength independently.

The LMG1205 is an enhancement over the LM5113. The LMG1205 takes the design of the LM5113 and includes start-up logic, level shifter, and power-off Vgs clamp enhancements to provide a more robust solution.

In addition, the strong sink capability of the LM5113 maintains the gate in the low state, preventing unintended turnon during switching. The LM5113 can operate up to several MHz. The LM5113 is available in a standard WSON-10 pin package and a 12-bump DSBGA package. The WSON-10 pin package contains an exposed pad to aid power dissipation. The DSBGA package offers a compact footprint and minimized package inductance.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
LM5113 WSON (10) 4.00 mm × 4.00 mm
DSBGA (12) 2.00 mm × 2.00 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.