SNVS725I June   2011  – October 2019 LM5113

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Application Diagram
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input and Output
      2. 7.3.2 Start-Up and UVLO
      3. 7.3.3 HS Negative Voltage and Bootstrap Supply Voltage Clamping
      4. 7.3.4 Level Shift
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 VDD Bypass Capacitor
        2. 8.2.2.2 Bootstrap Capacitor
        3. 8.2.2.3 Power Dissipation
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.1 Input and Output

The inputs are independently controlled with TTL input thresholds, and can withstand voltages up to 14 V regardless of the VDD voltage, which means it could be directly connected to the outputs of PWM controllers with up to 14-V power supply, saving a buffer stage between output of higher-voltage powered controller, for example LM5025 with 10 V, and input of the LM5113.

The output pulldown and pullup resistance of LM5113 is optimized for enhancement mode GaN FETs to achieve high frequency and efficient operation. The 0.6-Ω pulldown resistance provides a robust low impedance turnoff path necessary to eliminate undesired turnon induced by high dv/dt or high di/dt. The 2.1-Ω pullup resistance helps reduce the ringing and over-shoot of the switch node voltage. The split outputs of the LM5113 offer flexibility to adjust the turnon and turnoff speed by independently adding additional impedance in either the turnon path, the turnoff path, or both.

It is very important that the input signal of the two channels HI and LI, which has logic compatible threshold and hysteresis, must be tied to either VDD or VSS if they are not used. This inputs must not be left floating.

Additionally, the input signals avoid pulses shorter than 3 ns by using the input filter to the HI and LI input pins. The values and part numbers of the circuit components are shown in the Figure 16.

LM5113 input-filter-1-for-YZPR-high-side-input-filter-SNVS725.gifFigure 16. Input Filter 1 (High-Side Input Filter)

If short pulses or short delays are required, the circuit in Figure 17 is recommended.

LM5113 input-filter-snvs725-zp.gifFigure 17. Input Filter 1 for Short Pulses (High-Side Input Filter)