SNVS499I February   2007  – November 2023 LM5116

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Performance Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 High Voltage Start-Up Regulator
      2. 6.3.2 Enable
      3. 6.3.3 UVLO
      4. 6.3.4 Oscillator and Sync Capability
      5. 6.3.5 Error Amplifier and PWM Comparator
      6. 6.3.6 Ramp Generator
      7. 6.3.7 Current Limit
      8. 6.3.8 HO Output
      9. 6.3.9 Thermal Protection
    4. 6.4 Device Functional Modes
      1. 6.4.1 Soft-Start and Diode Emulation
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1  Custom Design with WEBENCH® Tools
        2. 7.2.2.2  Timing Resistor
        3. 7.2.2.3  Output Inductor
        4. 7.2.2.4  Current Sense Resistor
        5. 7.2.2.5  Ramp Capacitor
        6. 7.2.2.6  Output Capacitors
        7. 7.2.2.7  Input Capacitors
        8. 7.2.2.8  VCC Capacitor
        9. 7.2.2.9  Bootstrap Capacitor
        10. 7.2.2.10 Soft Start Capacitor
        11. 7.2.2.11 Output Voltage Divider
        12. 7.2.2.12 UVLO Divider
        13. 7.2.2.13 MOSFETs
        14. 7.2.2.14 MOSFET Snubber
        15. 7.2.2.15 Error Amplifier Compensation
        16. 7.2.2.16 Comprehensive Equations
          1. 7.2.2.16.1 Current Sense Resistor and Ramp Capacitor
          2. 7.2.2.16.2 Modulator Transfer Function
          3. 7.2.2.16.3 Error Amplifier Transfer Function
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Third-Party Products Disclaimer
      2. 8.1.2 Development Support
        1. 8.1.2.1 Custom Design with WEBENCH® Tools
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3.7 Current Limit

The LM5116 contains a current limit monitoring scheme to protect the circuit from possible over-current conditions. When set correctly, the emulated current sense signal is proportional to the buck switch current with a scale factor determined by the current limit sense resistor. The emulated ramp signal is applied to the current limit comparator. If the emulated ramp signal exceeds 1.6 V, the current cycle is terminated (cycle-by-cycle current limiting). Because the ramp amplitude is proportional to VIN - VOUT, if VOUT is shorted, there is an immediate reduction in duty cycle. To further protect the external switches during prolonged current limit conditions, an internal counter counts clock pulses when in current limit. When the counter detects 256 consecutive clock cycles, the regulator enters a low power dissipation hiccup mode of current limit. The regulator is shut down by momentarily pulling UVLO low, and the soft-start capacitor discharged. The regulator is restarted with a full soft-start cycle after UVLO charges back to 1.215 V. This process is repeated until the fault is removed. The hiccup off-time can be controlled by a capacitor to ground on the UVLO pin. In applications with low output inductance and high input voltage, the switch current can overshoot due to the propagation delay of the current limit comparator. If an overshoot must occur, the sample-and-hold circuit will detect the excess recirculating current. If the sample-and-hold DC level exceeds the internal current limit threshold, the buck switch will be disabled and skip pulses until the current has decayed below the current limit threshold. This approach prevents current runaway conditions due to propagation delays or inductor saturation because the inductor current is forced to decay following any current overshoot.

GUID-26759B8B-4113-418A-8203-F5A8355FE2F1-low.gif Figure 6-7 Current Limit and Ramp Circuit

Using a current sense resistor in the source of the low-side MOSFET provides superior current limit accuracy compared to RDS(ON) sensing. RDS(ON) sensing is far less accurate due to the large variation of MOSFET RDS(ON) with temperature and part-to-part variation. The CS and CSG pins must be Kelvin connected to the current sense resistor or MOSFET drain and source.

The peak current which triggers the current limit comparator is:

Equation 5. GUID-6A656DE8-5549-4359-BAA2-1B785E3E6006-low.gif

where

  • tON is the on-time of the high-side MOSFET

The 1.1-V threshold is the difference between the 1.6-V reference at the current limit comparator and the 0.5-V offset at the current sense amplifier. This offset at the current sense amplifier allows the inductor ripple current to go negative by 0.5 V / (A ✕ RS) when running full synchronous operation.

Current limit hysteresis prevents chatter around the threshold when VCCX is powered from VOUT. When 4.5 V < VCC < 5.8 V, the 1.6-V reference is increased to 1.72 V. The peak current which triggers the current limit comparator becomes:

Equation 6. GUID-07B9085C-5680-464B-87EA-7D9F6BC18FDE-low.gif

This has the effect of a 10% fold-back of the peak current during a short circuit when VCCX is powered from a 5-V output.