SNVS499I
February 2007 – November 2023
LM5116
PRODUCTION DATA
1
1
Features
2
Applications
3
Description
4
Pin Configuration and Functions
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
Recommended Operating Conditions
5.4
Thermal Information
5.5
Electrical Characteristics
5.6
Switching Characteristics
5.7
Typical Performance Characteristics
6
Detailed Description
6.1
Overview
6.2
Functional Block Diagram
6.3
Feature Description
6.3.1
High Voltage Start-Up Regulator
6.3.2
Enable
6.3.3
UVLO
6.3.4
Oscillator and Sync Capability
6.3.5
Error Amplifier and PWM Comparator
6.3.6
Ramp Generator
6.3.7
Current Limit
6.3.8
HO Output
6.3.9
Thermal Protection
6.4
Device Functional Modes
6.4.1
Soft-Start and Diode Emulation
7
Application and Implementation
7.1
Application Information
7.2
Typical Application
7.2.1
Design Requirements
7.2.2
Detailed Design Procedure
7.2.2.1
Custom Design with WEBENCH® Tools
7.2.2.2
Timing Resistor
7.2.2.3
Output Inductor
7.2.2.4
Current Sense Resistor
7.2.2.5
Ramp Capacitor
7.2.2.6
Output Capacitors
7.2.2.7
Input Capacitors
7.2.2.8
VCC Capacitor
7.2.2.9
Bootstrap Capacitor
7.2.2.10
Soft Start Capacitor
7.2.2.11
Output Voltage Divider
7.2.2.12
UVLO Divider
7.2.2.13
MOSFETs
7.2.2.14
MOSFET Snubber
7.2.2.15
Error Amplifier Compensation
7.2.2.16
Comprehensive Equations
7.2.2.16.1
Current Sense Resistor and Ramp Capacitor
7.2.2.16.2
Modulator Transfer Function
7.2.2.16.3
Error Amplifier Transfer Function
7.2.3
Application Curves
7.3
Power Supply Recommendations
7.4
Layout
7.4.1
Layout Guidelines
7.4.2
Layout Example
8
Device and Documentation Support
8.1
Device Support
8.1.1
Third-Party Products Disclaimer
8.1.2
Development Support
8.1.2.1
Custom Design with WEBENCH® Tools
8.2
Receiving Notification of Documentation Updates
8.3
Support Resources
8.4
Trademarks
8.5
Electrostatic Discharge Caution
8.6
Glossary
9
Revision History
10
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
PWP|20
MHTS001G
Thermal pad, mechanical data (Package|Pins)
PWP|20
PPTD289
Orderable Information
snvs499i_oa
snvs499i_pm
7.2.2
Detailed Design Procedure