8.3.1 Feedback Compensation

Open loop response of the regulator is defined as the product of modulator transfer function and feedback transfer function. When plotted on a dB scale, the open loop gain is shown as the sum of modulator gain and feedback gain.

The modulator transfer function includes a power stage transfer function with an embedded current loop and can be simplified as one pole and one zero system as shown in Equation 15.

Equation 15.

If the ESR of C_OUT (R_ESR) is very small, the modulator transfer function can be further simplified to a one pole system and the voltage loop can be closed with only two loop compensation components, R_COMP and C_COMP, leaving a single pole response at the crossover frequency. A single pole response at the crossover frequency yields a very stable loop with 90 degrees of phase margin.

The feedback transfer function includes the feedback resistor divider and loop compensation of the error amplifier. R_COMP, C_COMP and optional C_HF configure the error amplifier gain and phase characteristics and create a pole at origin, a low frequency zero and a high frequency pole. This is shown mathematically in Equation 16.

Equation 16.

The pole at the origin minimizes output steady state error. The low frequency zero should be placed to cancel the load pole of the modulator. The high frequency pole can be used to cancel the zero created by the output capacitor ESR or to decrease noise susceptibility of the error amplifier. By placing the low frequency zero an order of magnitude less than the crossover frequency, the maximum amount of phase boost can be achieved at the crossover frequency. The high frequency pole should be placed well beyond the crossover frequency since the addition of C_HF adds a pole in the feedback transfer function.

The crossover frequency (loop bandwidth) is usually selected between one twentieth and one fifth of the f_SW. In a simplified formula, the crossover frequency can be defined as:

Equation 17.

For higher crossover frequency, R_COMP can be increased, while proportionally decreasing C_COMP. Conversely, decreasing R_COMP while proportionally increasing C_COMP, results in lower bandwidth while keeping the same zero frequency in the feedback transfer function.

The sampled gain inductor pole is inversely proportional to the K factor, which is defined as:

Equation 18.

The maximum achievable loop bandwidth, in fact, is limited by this sampled gain inductor pole. In traditional current mode control, the maximum achievable loop bandwidth varies with input voltage. With the LM5117’s unique slope compensation scheme, the sampled gain inductor pole is independent of changes to the input voltage. This frees the user from additional concerns in wide varying input range applications and is an advantage of the LM5117.

If the sampled gain inductor pole or the ESR zero is close to the crossover frequency, it is recommended that the comprehensive formulas in Table 1 be used and the stability should be checked by a network analyzer. The modulator transfer function can be measured and the feedback transfer function can be configured for the desired open loop transfer function. If a network analyzer is not available, step load transient tests can be performed to verify acceptable performance. The step load goal is minimum overshoot/undershoot with a damped response.

8.3.2 Sub-Harmonic Oscillation

Peak current mode regulators can exhibit unstable behavior when operating above 50% duty cycle. This behavior is known as sub-harmonic oscillation and is characterized by alternating wide and narrow pulses at the SW pin. Sub-harmonic oscillation can be prevented by adding an additional voltage ramp (slope compensation) on top of the sensed inductor current shown in Figure 20. By choosing K≥1, the regulator will not be subject to sub-harmonic oscillation caused by a varying input voltage.

In time-domain analysis, the steady-state inductor current starts and ends at the same value during one clock cycle. If the magnitude of the end-of-cycle current error, dI₁, caused by an initial perturbation, dI₀, is less than the magnitude of dI₀ or dI₁/dI₀ > -1, the perturbation naturally disappears after a few cycles. When dI₁/dI₀ < -1, the initial perturbation does not disappear, resulting in sub-harmonic oscillation in steady-state operation.

Figure 30. Effect of Initial Perturbation when dl₁/dl₀ < -1

dI₁/dI₀ can be calculated by:

Equation 19.

The relationship between dI₁/dI₀ and K factor is illustrated graphically in Figure 31.

Figure 31. dl₁/dl₀ vs K Factor

The minimum value of K is 0.5. When K<0.5, the amplitude of dI₁ is greater than the amplitude of dI₀ and any initial perturbation results in sub-harmonic oscillation. If K=1, any initial perturbation will be removed in one switching cycle. This is known as one-cycle damping. When -1<dl₁/dl₀<0, any initial perturbation will be under-damped. Any perturbation will be over-damped when 0<dl₁/dl₀<1.

In the frequency-domain, Q, the quality factor of the sampling gain term in the modulator transfer function, is used to predict the tendency for sub-harmonic oscillation, which is defined as:

Equation 20.

The relationship between Q and K factor is illustrated graphically in Figure 32.

Figure 32. Sampling gain Q vs K Factor

The minimum value of K is 0.5 again. This is the same as time domain analysis result. When K<0.5, the regulator is unstable. High gain peaking at 0.5 results in sub-harmonic oscillation at F_SW/2. When K=1, one-cycle damping is realized. Q is equal to 0.673 at this point. A higher K factor may introduce additional phase shift by moving the sampled gain inductor pole closer to the crossover frequency, but will help reduce noise sensitivity in the current loop. The maximum allowable value of K factor can be calculated by the Maximum Crossover Frequency equation in Table 1.

8.3.3 Design Requirements

8.3.4 Timing Resistor R_T

Generally, higher frequency applications are smaller but have higher losses. Operation at 230 kHz was selected for this example as a reasonable compromise between small size and high efficiency. The value of R_T for 230 kHz switching frequency can be calculated from Equation 3 as follows:

Equation 21.

A standard value of 22.1 kΩ was chosen for R_T.

8.3.5 Output Inductor L_O

The maximum inductor ripple current occurs at the maximum input voltage. Typically, 20% to 40% of the full load current is a good compromise between core loss and copper loss of the inductor. Higher ripple current allows for a smaller inductor size, but places more of a burden on the output capacitor to smooth the ripple voltage on the output. For this example, a ripple current of 40% of 9 A was chosen. Knowing the switching frequency, maximum ripple current, maximum input voltage and the nominal output voltage, the inductor value can be calculated as follows:

Equation 22.

The closest standard value of 10 μH was chosen for L_O. Using the value of 10 μH for L_O, calculate I_PP again. This step is necessary if the chosen value of L_O differs significantly from the calculated value.

From Equation 11,

Equation 23.

At the minimum input voltage, this value is 1.04 A.

8.3.6 Diode Emulation Function

The DEMB pin is left floating since this example uses diode emulation to reduce the power loss under no load or light load conditions.

8.3.7 Current Sense Resistor R_S

The performance of the converter will vary depending on the K value. For this example, K = 1 was chosen to control sub-harmonic oscillation and achieve one-cycle damping. The maximum output current capability (I_OUT(MAX)) should be 20~50% higher than the required output current, to account for tolerances and ripple current. For this example, 130% of 9 A was chosen. The current sense resistor value can be calculated from Equation 9 and Equation 10 as follows:

Equation 24.

Equation 25.

A value of 7.41 mΩ was realized for R_S by placing an additional 0.1-Ω sense resistor in parallel with 8 mΩ. The sense resistor must be rated to handle the power dissipation at maximum input voltage when current flows through the low-side NMOS for the majority of the PWM cycle. The maximum power dissipation of R_S can be calculated as:

Equation 26.

Equation 27.

The worst case peak inductor current under the output short condition can be calculated from Equation 12 as follows:

Equation 28.

where

• t_ON(MIN) is normally 100ns

8.3.8 Current Sense Filter R_CS and C_CS

The LM5117 itself is not affected by the large leading edge spike because it samples valley current just prior to the onset of the high-side switch. A current sense filter is used to minimize a noise injection from any external noise sources. In general, a current sense filter is not necessary. In this example, a current sense filter is not used

Adding R_CS resistor changes the current sense amplifier gain which is defined as A_S=10 k / (1 k+R_CS). A small value of R_CS resistor below 100 Ω is recommended to minimize the gain change which is caused by the temperature coefficient difference between internal and external resistors.

8.3.9 Ramp Resistor R_RAMP and Ramp Capacitor C_RAMP

The positive slope of the inductor current ramp signal is emulated by R_RAMP and C_RAMP. For this example, the value of C_RAMP was set at the standard capacitor value of 820 pF. With the inductor, sense resistor and the K factor selected, the value of R_RAMP can be calculated from Equation 4 as follows:

Equation 29.

Equation 30.

The standard value of 165 kΩ was selected for R_RAMP.

8.3.10 UVLO Divider R_UV2, R_UV1 and C_FT

The desired startup voltage and the hysteresis are set by the voltage divider R_UV1 and R_UV2. Capacitor C_FT provides filtering for the divider. For this design, the startup voltage was set to 14 V, 1 V below V_IN(MIN). V_HYS was set to 2 V. The value of R_UV1, R_UV2 can be calculated from Equation 1 and Equation 2 as follows:

Equation 31.

Equation 32.

The standard value of 100 kΩ was selected for R_UV2. R_UV1 was selected to be 9.76 kΩ. A value of 47 pF was chosen for C_FT.

8.3.11 VCC Disable and External VCC Supply

The 12-V output voltage allows the external VCC supply configuration as shown in Figure 16. In this example, VCCDIS can be left floating since V_OUT is higher than VCC regulator set-point level.

8.3.12 Power Switches Q_H and Q_L

Selection of the power NMOS devices is governed by the same trade-offs as switching frequency. Breaking down the losses in the high-side and low-side NMOS devices is one way to compare the relative efficiencies of different devices. Losses in the power NMOS devices can be broken down into conduction loss, gate charging loss, and switching loss.

Conduction loss P_DC is approximately:

Equation 33.

Equation 34.

where

• D is the duty cycle
• the factor of 1.3 accounts for the increase in the NMOS device on-resistance due to heating

Alternatively, the factor of 1.3 can be eliminated and the high temperature on-resistance of the NMOS device can be estimated using the R_DS(ON) vs Temperature curves in the MOSFET datasheet.

Gate charging loss (P_GC) results from the current driving the gate capacitance of the power NMOS devices and is approximated as:

Equation 35.

Qg refers to the total gate charge of an individual NMOS device, and ‘n’ is the number of NMOS devices. Gate charge loss differs from conduction and switching losses in that the actual dissipation occurs in the controller IC. Switching loss (P_SW) occurs during the brief transition period as the high-side NMOS device turns on and off. During the transition period both current and voltage are present in the channel of the NMOS device. The switching loss can be approximated as:

Equation 36.

t_R and t_F are the rise and fall times of the high-side NMOS device. The rise and fall times are usually mentioned in the MOSFET datasheet or can be empirically observed with an oscilloscope. Switching loss is calculated for the high-side NMOS device only. Switching loss in the low-side NMOS device is negligible because the body diode of the low-side NMOS device turns on before and after the low-side NMOS device switches. For this example, the maximum drain-to-source voltage applied to either NMOS device is 55 V. The selected NMOS devices must be able to withstand 55 V plus any ringing from drain to source and must be able to handle at least the VCC voltage plus any ringing from gate to source.

8.3.13 Snubber Components R_SNB and C_SNB

A resistor-capacitor snubber network across the low-side NMOS device reduces ringing and spikes at the switching node. Excessive ringing and spikes can cause erratic operation and can couple noise to the output voltage. Selecting the values for the snubber is best accomplished through empirical methods. First, make sure the lead lengths for the snubber connections are very short. Start with a resistor value between 5 and 50 Ω. Increasing the value of the snubber capacitor results in more damping, but higher snubber losses. Select a minimum value for the snubber capacitor that provides adequate damping of the spikes on the switch waveform at heavy load. A snubber may not be necessary with an optimized layout.

8.3.14 Bootstrap Capacitor C_HB and Bootstrap Diode D_HB

The bootstrap capacitor between the HB and SW pin supplies the gate current to charge the high-side NMOS device gate during each cycle’s turn-on and also supplies recovery charge for the bootstrap diode. These current peaks can be several amperes. The recommended value of the bootstrap capacitor is at least 0.1 μF. C_HB should be a good quality, low ESR, ceramic capacitor located at the pins of the IC to minimize potentially damaging voltage transients caused by trace inductance. The absolute minimum value for the bootstrap capacitor is calculated as:

Equation 37.

where

• Qg is the high-side NMOS gate charge
• ΔV_HB is the tolerable voltage droop on C_HB, which is typically less than 5% of VCC or 0.15 V conservatively

A value of 0.47 μF was selected for this design.

8.3.15 VCC Capacitor C_VCC

The primary purpose of the VCC capacitor (C_VCC) is to supply the peak transient currents of the LO driver and bootstrap diode as well as provide stability for the VCC regulator. These peak currents can be several amperes. The recommended value of C_VCC should be no smaller than 0.47μF, and should be a good quality, low ESR, ceramic capacitor. C_VCC should be placed at the pins of the IC to minimize potentially damaging voltage transients caused by trace inductance. A value of 1 μF was selected for this design.

8.3.16 Output Capacitor C_O

The output capacitors smooth the output voltage ripple caused by inductor ripple current and provide a source of charge during transient loading conditions. For this design example, a 470-μF electrolytic capacitor with maximum 20mΩ ESR was selected as the main output capacitor. The fundamental component of the output ripple voltage with maximum ESR is approximated as:

Equation 38.

Equation 39.

Additional low ERS / ESL ceramic capacitors can be placed in parallel with the main output capacitor to further reduce the output voltage ripple and spikes. In this example, two 22μF capacitors were added.

8.3.17 Input Capacitor C_IN

The regulator input supply voltage typically has high source impedance at the switching frequency. Good quality input capacitors are necessary to limit the ripple voltage at the VIN pin while supplying most of the switch current during the on-time. When the high-side NMOS device turns on, the current into the device steps to the valley of the inductor current waveform, ramps up to the peak value, and then drops to the zero at turnoff. The input capacitor should be selected for RMS current rating and minimum ripple voltage. A good approximation for the required ripple current rating necessary is I_RMS > I_OUT / 2.

In this example, seven 3.3μF ceramic capacitors were used. With ceramic capacitors, the input ripple voltage will be triangular. The input ripple voltage can be approximated as:

Equation 40.

Equation 41.

Capacitors connected in parallel should be evaluated for RMS current rating. The current will split between the input capacitors based on the relative impedance of the capacitors at the switching frequency.

8.3.18 VIN Filter R_VIN, C_VIN

An R-C filter (R_VIN, C_VIN) on VIN is optional. The filter helps to prevent faults caused by high frequency switching noise injection into the VIN pin. A 0.47-μF ceramic capacitor is used for C_VIN in the example. R_VIN is selected to be 3.9 Ω.

8.3.19 Soft-Start Capacitor C_SS

The capacitor at the SS pin (C_SS) determines the soft-start time (t_SS), which is the time for the output voltage to reach the final regulated value. The t_SS for a given C_SS can be calculated from Equation 8 as follows:

Equation 42.

For this example, a value of 0.1 μF was chosen for a soft-start time of 8 ms.

8.3.20 Restart Capacitor C_RES

The capacitor at the RES pin (C_RES) determines t_RES, which is the time the LM5117 remains off before a restart attempt is made in hiccup mode current limiting. t_RES for a given C_RES can be calculated from Equation 13 as follows:

Equation 43.

For this example, a value of 0.47 μF was chosen for a restart time of 59 ms.

8.3.21 Output Voltage Divider R_FB2 and R_FB1

R_FB1 and R_FB2 set the output voltage level. The ratio of these resistors is calculated as:

Equation 44.

The ratio between R_COMP and R_FB2 determines the mid-band gain, A_{FB_MID}. A larger value for R_FB2 may require a corresponding larger value for R_COMP. R_FB2 should be large enough to keep the total divider power dissipation small. 4.99 kΩ was chosen for R_FB2 in this example, which results in a R_FB1 value of 357 Ω for 12-V output.

8.3.22 Loop Compensation Components C_COMP, R_COMP and C_HF

R_COMP, C_COMP and C_HF configure the error amplifier gain and phase characteristics to produce a stable voltage loop. For a quick start, follow the 4 steps listed below.

STEP1: Select f_CROSS

By selecting one tenth of the switching frequency, f_CROSS is calculated as follows:

Equation 45.

STEP2: Determine required R_COMP

Knowing f_CROSS, R_COMP is calculated as follows:

Equation 46.

Equation 47.

The standard value of 27.4kΩ was selected for R_COMP

STEP3: Determine C_COMP to cancel load pole

Knowing R_COMP, C_COMP is calculated as follows:

Equation 48.

The standard value of 22nF was selected for C_COMP

STEP4: Determine C_HF to cancel ESR zero

Knowing R_COMP and C_COMP, C_HF is calculated as follows:

Equation 49.

Equation 50.

Half of the maximum ESR is assumed as a typical ESR. The standard value of 180pF was selected for C_HF.

Table 1. LM5117 Frequency Analysis Formulas

	SIMPLE FORMULA	COMPREHENSIVE FORMULA(1)
MODULATOR TRANSFER FUNCTION
Modulator DC Gain
ESR Zero
ESR Pole	Not considered
Dominant Load Pole
Sampled Gain Inductor Pole	Not considered
Quality Factor	Not considered
Sub-harmonic Double Pole	Not considered
K Factor
FEEDBACK TRANSFER FUNCTION
Feedback DC Gain
Mid-band Gain
Low Frequency Zero
High Frequency Pole
OPEN-LOOP RESPONSE
Cross Over Frequency (Open Loop Bandwidth)
Maximum Cross Over Frequency		The frequency at which 45° phase shift occurs in modulator phase characteristics.

8.4.1 Constant Current Regulator

The LM5117 can be configured as a constant current regulator by using the current monitor feature (CM) as the feedback input. A voltage divider at the VCCDIS pin from VOUT to AGND can be used to protect against output over-voltage. When the VCCDIS pin voltage is greater than the VCCDIS threshold, the controller disables the VCC regulator and the VCC pin voltage decays. When the VCC pin voltage is less than the VCC UV threshold, both HO and LO outputs stop switching. Due to the time delay required for VCC to decay below the VCC UV threshold, the over-voltage protection operates in hiccup mode. See Figure 35.

Figure 35. Constant Current Regulator With Hiccup Mode Output OVP

8.4.2 Constant Voltage and Constant Current Regulator

The LM5117 also can be configured as a constant voltage and constant current regulator, known as CV+CC regulator. In this configuration, there is much less variation in the current limiting as compared to peak cycle-by-cycle current limiting of the inductor current. The LMV431 and the PNP transistor create a voltage-to-current amplifier in the current loop. This amplifier circuitry does not affect the normal operation when the output current is less than the current limit set-point. When the output current is greater than the set-point, the PNP transistor sources a current into C_RAMP and increases the positive slope of emulated inductor current ramp until the output current is less than or equal to the current limit set-point. See Figure 36 and Figure 37.

Figure 36. Constant Voltage Regulator with Accurate Current Limit

Figure 37. Current Limit Comparison